Patents by Inventor Marcus Pawley

Marcus Pawley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553557
    Abstract: In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding from a first side face of the dielectric core layer. The contact layer includes an electrically insulating layer and at least one contact pad arranged on the electrically insulating layer. The at least one contact pad is electrically coupled with the power semiconductor device.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Patent number: 10192846
    Abstract: In an embodiment, a method includes inserting an electronic component including a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board. The inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Patent number: 10032688
    Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: July 24, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley
  • Patent number: 9917024
    Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley
  • Publication number: 20160322271
    Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventors: Martin Standing, Marcus Pawley
  • Patent number: 9418925
    Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Standing, Marcus Pawley
  • Publication number: 20160128198
    Abstract: In an embodiment, a method includes inserting an electronic component including a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board. The inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 5, 2016
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Publication number: 20160126210
    Abstract: In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding from a first side face of the dielectric core layer. The contact layer includes an electrically insulating layer and at least one contact pad arranged on the electrically insulating layer. The at least one contact pad is electrically coupled with the power semiconductor device.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 5, 2016
    Inventors: Martin Standing, Marcus Pawley, Andrew Roberts, Robert Clarke
  • Publication number: 20160005673
    Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 7, 2016
    Inventors: Martin Standing, Marcus Pawley
  • Publication number: 20160005684
    Abstract: In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode arranged on the first major surface and a second major surface that opposes the first major surface. One or more slots are arranged within the dielectric core layer adjacent the semiconductor die and a redistribution structure electrically couples the first electrode to a component contact pad arranged adjacent the second major surface of the semiconductor die. The semiconductor die is embedded in the dielectric core layer and a portion of the redistribution structure is arranged on side walls of the slot.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 7, 2016
    Inventors: Martin Standing, Marcus Pawley