Patents by Inventor Marcus Perrett

Marcus Perrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11599944
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: March 7, 2023
    Assignee: FIXNETIX LIMITED
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Patent number: 11393032
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, systems and methods can be configured to receive a market order data packet, wherein the market order data packet comprises order information for a market order to be made at a liquidity venue. The market order data packet comprises a header portion and a payload portion, and the header portion comprises at least a portion of the order information. An order symbol is determined based on order symbol information in the header portion. Risk parameters are retrieved associated with the order symbol. It is determined whether or not a risk threshold is exceeded based on the risk parameters and the order information. A final market order data packet is generated for transmission to the liquidity venue based on the determining whether the risk threshold is exceeded.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 19, 2022
    Assignee: FIXNETIX LIMITED
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Patent number: 11367136
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: June 21, 2022
    Assignee: FIXNETIX LIMITED
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20220076336
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 10, 2022
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20200320625
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, systems and methods can be configured to receive a market order data packet, wherein the market order data packet comprises order information for a market order to be made at a liquidity venue. The market order data packet comprises a header portion and a payload portion, and the header portion comprises at least a portion of the order information. An order symbol is determined based on order symbol information in the header portion. Risk parameters are retrieved associated with the order symbol. It is determined whether or not a risk threshold is exceeded based on the risk parameters and the order information. A final market order data packet is generated for transmission to the liquidity venue based on the determining whether the risk threshold is exceeded.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20200193517
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Application
    Filed: October 30, 2019
    Publication date: June 18, 2020
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20200160446
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Application
    Filed: September 30, 2019
    Publication date: May 21, 2020
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20190392519
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, systems and methods can be configured to receive a market order data packet, wherein the market order data packet comprises order information for a market order to be made at a liquidity venue. The market order data packet comprises a header portion and a payload portion, and the header portion comprises at least a portion of the order information. An order symbol is determined based on order symbol information in the header portion. Risk parameters are retrieved associated with the order symbol. It is determined whether or not a risk threshold is exceeded based on the risk parameters and the order information. A final market order data packet is generated for transmission to the liquidity venue based on the determining whether the risk threshold is exceeded.
    Type: Application
    Filed: January 15, 2019
    Publication date: December 26, 2019
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20170032462
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, systems and methods can be configured to receive a market order data packet, wherein the market order data packet comprises order information for a market order to be made at a liquidity venue. The market order data packet comprises a header portion and a payload portion, and the header portion comprises at least a portion of the order information. An order symbol is determined based on order symbol information in the header portion. Risk parameters are retrieved associated with the order symbol. It is determined whether or not a risk threshold is exceeded based on the risk parameters and the order information. A final market order data packet is generated for transmission to the liquidity venue based on the determining whether the risk threshold is exceeded.
    Type: Application
    Filed: July 28, 2016
    Publication date: February 2, 2017
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Publication number: 20160371777
    Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 22, 2016
    Inventors: Marcus Perrett, Paul Ellis, Hugh Hughes
  • Patent number: 9117502
    Abstract: An embedded hardware-based risk system is provided that has an apparatus and method for the management of unique alpha-numeric order message identifiers within DDR memory space restrictions. The apparatus provides a new design for assigning orders (CLOrID) to memory and the method thereof specifically with the intention to not impact latency until memory is over 90% full.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: August 25, 2015
    Assignee: FIXNETIX LTD.
    Inventors: Hugh Hughes, Paul Ellis, Alasdair Moore, Marcus Perrett