Abstract: A processing system for distributing work in a computing environment arranges nodes in a network topology. Each node comprises upstream and downstream ports for receiving and sending packets, and ingress or egress ports for accepting new entries or forwarding packets to functional units. Nodes evaluate received packets for local processing, removing them for processing or forwarding to the next node. The system implements flow control at ingress ports, arbitrates between multiple ingress ports when the upstream port is idle, and distributes work locally to connected egress ports. Packets are inspected to determine suitability for processing by connected functional units. This efficient system enables flexible work distribution strategies in homogeneous and heterogeneous networks, reducing the need for repeaters and long wires on integrated circuits.

Abstract: A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.

Abstract: A system and method for updating a bounding volume hierarchy (BVH) comprises a processor, memory, BVH update module, and feedback path. The feedback path returns a BVH quality estimate during the update, enabling estimation of box overlap to determine tree degradation. The system stores one value per BVH node describing original overlap volume of children, tracks this value as the tree deforms, and sends a rebuild indication when a threshold is reached. It can store a child-child overlap matrix and gather information on preferred axis swap, aspect ratio changes, and active triangles. The feedback path provides information to avoid rebuilding undegraded tree parts.

Abstract: A graphics processor accelerates rasterization using a bounding volume hierarchy (BVH) traversal unit. The unit performs intersection tests between BVH nodes and a view frustum, identifies visible nodes, and sends geometry content of visible leaf nodes to a rasterizer. Nodes are transformed into view space and clipped against the frustum. Non-intersecting nodes are discarded while traversal continues for intersecting nodes. Fully contained nodes bypass clipping. Visible leaf nodes are sorted for optimized depth testing. Non-overlapping nodes enable parallel rendering. The view frustum is subdivided into screen-aligned regions for dedicated rasterization. This approach enhances performance through efficient visibility determination and parallelism.

Abstract: A processing system comprises a memory and a processor configured to store multiple data elements of non-power-of-two bit width across plural registers with power-of-two bit width. The processor stores each bit of the data elements in separate registers, with the first bit in a first register, second bit in a second register, and so on. Arithmetic operations are performed on corresponding bits across registers. The number of data elements equals the register bit width. An arithmetic logic unit concurrently operates on the data elements using bits stored across registers. The system enables efficient storage and processing of low-precision values, optimizing cache usage and reducing wasted bits. This novel approach improves performance for applications like artificial intelligence using narrow data types.

Abstract: A processor for raytracing is provided, the processor being configured to: generate a bounding volume hierarchy, quantize at least one bounding box associated with the bounding volume hierarchy, dynamically allocate a number of quantization bits for at least one of x, y, and z dimensions of the at least one bounding box, wherein a variable number of quantization bits per dimension is used in the quantization.

Abstract: A system and method for synchronizing multiple graphics processing units (GPUs) connected via an interconnect link. The system implements a synchronization protocol on top of memory semantics provided by the interconnect link. Each GPU maps memory apertures for other GPUs. The protocol executes a broadcast into all aperture ranges from one GPU with appropriate memory semantics and synchronizes other GPUs by waiting for the memory write to become visible. A command processor performs synchronization logic for each GPU. The method establishes communication between GPUs, implements the protocol, maps memory apertures, and executes the synchronization process. This approach leverages existing infrastructure for efficient, decentralized multi-GPU synchronization using N messages for N GPUs.

Abstract: A processing system and method for compressing image data divides an image into pixel blocks. For each block, it computes minimum and maximum pixel values, determines bits needed to store pixel-to-minimum differences, calculates those differences, and stores them as bit-planes in memory. The system can store minimum/maximum values in metadata and compute absolute differences between them. Bit requirements are calculated using log 2(delta+1) rounded up. Bit-planes may be compressed for streaming access or fixed-size allocated for random access. The approach enables bandwidth reduction while maintaining random access or storage reduction with streaming access. This novel technique provides efficient image compression with flexible access options.