Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: The invention relates to a semiconductor device (10) with a substrate and a semiconductor body (1) comprising a first FET (3) with a source (2) and a drain (3) that are provided with connection regions (2B, 3B) of a metal silicide, and that are connected to source and drain extensions (2A, 3A) bordering a channel region (4) below a gate (6) and having a smaller thickness and a lower doping concentration than the source (2) and the drain (3). The source (2) and drain (3) and the source and drain extensions (2A, 3A) are connected to each other by means of an intermediate region (2C, 3C) of the first conductivity type having a thickness and a doping concentration ranging between the thickness and doping concentration of the source (2) and drain (3) and the extensions (2A, 3A) thereof.

Abstract: A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

Abstract: A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Abstract: A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a different work function. The work function of each transistor type is determined by selecting a thickness of a corresponding semiconductor gate electrode and a thermal budget of a first thermal step such that, during silicidation, different silicide phases are obtained on the nMOS and the pMOS transistors. The work function of each type of transistor can be adjusted by selectively doping the semiconductor material prior to the formation of the silicide.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material.

Abstract: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide.

Abstract: One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.