Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.

Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

Abstract: A method of access control in an electronic apparatus comprising at least one device and a shared memory, external to the said devices, which are connected by at least one communication bus. In one embodiment, a memory access control unit receives an instruction for access to the memory. The validity of the received operation is verified. If it is valid, the operation is carried out. Otherwise, the operation is not executed and no corresponding signal or instruction is produced. In response to invalid read operations, dummy data may be returned. This “silent” blocking of the operation makes it possible to control devices with DMA capability.

Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.

Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.