Patents by Inventor Marcus Volp
Marcus Volp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230393945Abstract: The present invention pertains to electronics (circuits and systems comprising such circuits, specifically like tiled multi- and manycore systems) for use in increased radiation environments. The invention provides (operating) methods and apparatuses (systems) for mitigating radiation effects in the (main) circuits (also denoted tiles) defining these apparatuses by adapting those or providing those with additional building blocks, enabling use of a depowering technique The invention also mitigates radiation effects in those building blocks (circuits or subcircuits) of the apparatuses themselves. The invention enables to retain full functionality on those resources of the chip that are not currently undergoing a depowering cycle, hence avoids power cycling those all simultaneously.Type: ApplicationFiled: January 28, 2022Publication date: December 7, 2023Inventors: Rafal GRACZYK, Marcus VÖLP, Paulo ESTEVES-VERÍSSIMO
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Patent number: 11657899Abstract: Genomics information such as DNA, RNA and proteins carry a wealth of sensitive information, the exposure of which risks compromising the privacy and/or business interest of individuals and companies. An apparatus, a system and methods are disclosed for protecting sensitive genomic information either as it is produced by a sequencing machine or immediately therafter, then throughout the whole genomic workflow. Raw genomic data (“reads”) is detected and classified according to sensitivity. Reads are decomposed by excising the number and type of detected sensitive base or base pairs in less sensitive or insensitive parts of the read. The genomic workflow processes the excised information locally or in a distributed fashion, preferably within trusted execution environments for increased security.Type: GrantFiled: September 26, 2018Date of Patent: May 23, 2023Assignee: Université du LuxembourgInventors: Paulo Esteves-Veríssimo, Marcus Völp, Jérémie Decouchant, Maria Fernandes
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Patent number: 11416617Abstract: There is disclosed a computing/data processing device comprising: a plurality of computing units, each computing unit comprising a computing resource; the computing device comprising at least three computing units, each computing unit comprising a/the same computing resource; each computing unit further comprising a computing unit access manager, each unit access manager being adapted to control access to the computing resource of the respective computing unit in response to at least one request; wherein, the computing unit access manager only allows a response to the at least one request if a majority of the computing units provide a same response to the at least one request; and wherein, the computing device comprising a network-on-a-chip, is provided on a chip and/or comprises an integrated chip (IC) or microprocessor. The IC beneficially comprises a Field-Programmable Gate Array (FPGA) device.Type: GrantFiled: February 8, 2018Date of Patent: August 16, 2022Assignee: Université du LuxembourgInventors: Marcus Völp, Paulo Esteves-Veríssimo, Jérémie Decouchant, Vincent Rahli, Francisco Rocha
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Patent number: 11176256Abstract: A capability-based data processing architecture (100) integrating an attesting module (120) are disclosed, together with subroutines for: securing the booting phase of a replicated or unreplicated subsystem (150) of computing units (130, 140) in the architecture and attesting to same; for adding and removing computing units (140) to and from booted systems 150; for relabelling authentication tokens when the booted subsystem (150) comprises computing units; for sealing and unsealing a memory storing data structures that are processed by the other subroutines described herein; and for recovering a booted subsystem (150) beset by faults.Type: GrantFiled: May 17, 2019Date of Patent: November 16, 2021Assignee: Université du LuxembourgInventors: Marcus Völp, Paulo Esteves-Veríssimo
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Publication number: 20210081535Abstract: A capability-based data processing architecture (100) integrating an attesting module (120) are disclosed, together with subroutines for: securing the booting phase of a replicated or unreplicated subsystem (150) of computing units (130, 140) in the architecture and attesting to same; for adding and removing computing units (140) to and from booted systems 150; for relabelling authentication tokens when the booted subsystem (150) comprises computing units; for sealing and unsealing a memory storing data structures that are processed by the other subroutines described herein; and for recovering a booted subsystem (150) beset by faults.Type: ApplicationFiled: May 17, 2019Publication date: March 18, 2021Inventors: Marcus Völp, Paulo Esteves-Veríssimo
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Publication number: 20200234794Abstract: Genomics information such as DNA, RNA and proteins carry a wealth of sensitive information, the exposure of which risks compromising the privacy and/or business interests of individuals and companies. An apparatus, a system and methods are disclosed for protecting sensitive genomic information either as it is produced by a sequencing machine or immediately thereafter, then throughout the whole genomic workflow. Raw genomic data (“reads”) is detected and classified according to sensitivity. Reads are decomposed by excising the number and type of detected sensitive base or base pairs in less sensitive or insensitive parts of the read. The genomic workflow processes the excised information locally or in a distributed fashion, preferably within trusted execution environments for increased security.Type: ApplicationFiled: September 26, 2018Publication date: July 23, 2020Inventors: Paulo Esteves-Veríssimo, Marcus Völp, Jérémie Decouchant, Maria Fernandes
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Publication number: 20200175168Abstract: There is disclosed a computing/data processing device comprising: a plurality of computing units, each computing unit comprising a computing resource; the computing device comprising at least three computing units, each computing unit comprising a/the same computing resource; each computing unit further comprising a computing unit access manager, each unit access manager being adapted to control access to the computing resource of the respective computing unit in response to at least one request; wherein, the computing unit access manager only allows a response to the at least one request if a majority of the computing units provide a same response to the at least one request; and wherein, the computing device comprising a network-on-a-chip, is provided on a chip and/or comprises an integrated chip (IC) or microprocessor. The IC beneficially comprises a Field-Programmable Gate Array (FPGA) device.Type: ApplicationFiled: February 8, 2018Publication date: June 4, 2020Inventors: Marcus Völp, Paulo Esteves-Veríssimo, Jérémie Decouchant, Vincent Rahli, Francisco Rocha
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Patent number: 7730544Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.Type: GrantFiled: October 6, 2004Date of Patent: June 1, 2010Assignee: STMicroelectronics SAInventor: Marcus Volp
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Patent number: 7657034Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.Type: GrantFiled: October 14, 2004Date of Patent: February 2, 2010Assignee: STMicroelectronics SAInventors: Marcus Völp, Claude Anguille
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Patent number: 7624261Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.Type: GrantFiled: May 11, 2006Date of Patent: November 24, 2009Assignee: STMicroelectronics S.A.Inventor: Marcus Volp
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Publication number: 20070113088Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.Type: ApplicationFiled: May 11, 2006Publication date: May 17, 2007Applicant: STMicroelectronics S.A.Inventor: Marcus Volp
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Publication number: 20050182909Abstract: A method of access control in an electronic apparatus comprising at least one device and a shared memory, external to the said devices, which are connected by at least one communication bus. In one embodiment, a memory access control unit receives an instruction for access to the memory. The validity of the received operation is verified. If it is valid, the operation is carried out. Otherwise, the operation is not executed and no corresponding signal or instruction is produced. In response to invalid read operations, dummy data may be returned. This “silent” blocking of the operation makes it possible to control devices with DMA capability.Type: ApplicationFiled: December 22, 2004Publication date: August 18, 2005Applicant: STMicroelectronics S.A.Inventors: Marcus Volp, William Orlando
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Publication number: 20050138403Abstract: For the encryption of data to be stored in a memory external to a circuit, provision is made to store in the external memory encrypted data words in association with an initialization vector and a key identifier associated with a secret key that has served to encrypt same.Type: ApplicationFiled: October 14, 2004Publication date: June 23, 2005Applicant: STMicroelectronics SAInventors: Marcus Volp, Claude Anguille
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Publication number: 20050081020Abstract: A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.Type: ApplicationFiled: October 6, 2004Publication date: April 14, 2005Applicant: STMicroelectronics S.A.Inventor: Marcus Volp