Abstract: It is provided a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries of an apparatus, causing the one or more processing circuitries to perform locally on the apparatus a method. The method includes receiving configuration inputs for a target semiconductor device, the configuration inputs comprising a device identifier, one or more safety-critical parameters, and profile-specific operational parameters for one or more semiconductor device configuration profiles. The method further includes generating a first set of configuration data for programming into a non-volatile one-time programmable memory of the target semiconductor device. The method further includes generating a second set of configuration data for a non-volatile rewritable memory of the target semiconductor device.

Abstract: It is provided a non-transitory computer-readable medium storing instructions that, when executed by a processing circuitry of an apparatus, causing the processing circuitry to perform locally on the apparatus a method. The method includes transmitting, to a boot controller of the computing system, a request to initiate a single-block transfer of full configuration data corresponding to the firmware of the component. The request comprises a destination address within a local memory of the component and a size of the configuration data. The method further includes receiving, from the boot controller, an acknowledgement indicating that the full configuration data has been loaded as a single block into the local memory at the destination address. The method further includes in response to the acknowledgement, parsing the single block of the full configuration data residing in the local memory to apply one or more configuration settings for the component.

Abstract: Some aspects of the present disclosure relate to a power management apparatus for a memory subsystem of a graphics processing unit, the power management apparatus comprising first interface circuitry for communicating with a system firmware of a host computer hosting the graphics processing unit, second interface circuitry for communicating with one or more components of the memory subsystem of the graphics processing unit, processor circuitry configured to obtain a memory subsystem control input from the system firmware, trigger execution of a sequence of operations in response to the memory subsystem control input, and provide a memory subsystem control output to the system firmware based on a result of the sequence of operations.

Abstract: It is provided an apparatus comprising interface circuitry configured to communicate with one or more memory controllers. The apparatus further comprises machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive a request from a management component to initiate collection of telemetry data from one or more memory devices. The machine-readable instructions further include instructions to, in response to the request, send a command to the one or more memory controllers to cause the at least one memory controller to read the telemetry data from one or more memory devices. The machine-readable instructions further include instructions to receive the telemetry data from the at least one memory controller, to stage the telemetry data, and to send an acknowledgement to the management component.

Abstract: Provided is an apparatus, a device, a method, a computer program, and a non-transitory, computer-readable medium comprising a program code for a computer system, as well as a computer system. An apparatus (10) for a computer system (100) comprises memory circuitry (11) for storing information identifying at least one defective memory hardware location, and one or more hardware address determination circuitries (12, 13) configured to determine a mapping between a physical memory address and a hardware location address of corresponding memory (101, 102), wherein the one or more hardware address determination circuitries are configured to adapt the mapping at run-time upon obtaining updated information identifying at least one defective memory hardware location.

Abstract: Systems and methods are disclosed for serial wire timer distribution in an SoC. For example, some methods may include adding an offset to a current timestamp to obtain an offset timestamp; serially transmitting the offset timestamp on a first conductor according to a functional-logic clock signal; receiving the offset timestamp via the first conductor; and writing the offset timestamp to a timestamp register at a time according to an edge of a fixed-frequency reference clock signal on a second conductor.

Abstract: Embodiments of the present disclosure may relate to the existence of a unique value associated with each PCIe function or device that is readable from two or more PCIe functions, or from a CPU running system software. Embodiments enable system software to identify which PCIe functions have private or hidden connections. In addition, embodiments may allow system software to differentiate among multiple identical instances of PCIe add-in components that have associations. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.

Abstract: Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.

Abstract: Embodiments of the present disclosure may relate to the existence of a unique value associated with each PCIe function or device that is readable from two or more PCIe functions, or from a CPU running system software. Embodiments enable system software to identify which PCIe functions have private or hidden connections. In addition, embodiments may allow system software to differentiate among multiple identical instances of PCIe add-in components that have associations. Other embodiments may be described and/or claimed.