Patents by Inventor Marcy E. Byers
Marcy E. Byers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138050Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.Type: GrantFiled: March 14, 2019Date of Patent: October 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
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Publication number: 20190391815Abstract: An information handling system and method is disclosed for processing information that in an embodiment includes at least one processor; at least one queue associated with the processor for holding instructions; and at least one age matrix associated with the queue for determining the relative age of the instructions held within the queue, including in situations where if multiple instructions enter the queue at the same time, age comparison calculations are first performed by comparing each simultaneous incoming instruction independently to instructions already in the queue, and then performing age calculations between the simultaneous incoming instructions. In one aspect, if the incoming instruction is older than any in-thread instruction already in the queue, then assigning for the older in-thread instruction in the age matrix the age of the next youngest in-thread instruction already in the queue.Type: ApplicationFiled: June 21, 2018Publication date: December 26, 2019Inventors: Elizabeth McGlone, Marcy E. Byers, Robert A. Cordes
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Patent number: 10387154Abstract: Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.Type: GrantFiled: March 14, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: James W. Bishop, Marcy E. Byers, Steven R. Carlough, Paul M. Kennedy, Albert J. Van Norstrand, Jr., Phillip G. Williams
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Publication number: 20190213055Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: BRIAN D. BARRICK, JAMES W. BISHOP, MARCY E. BYERS, SUNDEEP CHADHA, CLIFF KUCHARSKI, DUNG Q. NGUYEN, DAVID R. TERRY, JING ZHANG
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Patent number: 10318356Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.Type: GrantFiled: March 31, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
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Patent number: 10223196Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.Type: GrantFiled: November 7, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Brian D. Barrick, James W. Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra, Dung Q. Nguyen, David R. Terry
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Publication number: 20180095820Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.Type: ApplicationFiled: November 7, 2017Publication date: April 5, 2018Inventors: Brian D. Barrick, James W. Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra, Dung Q. Nguyen, David R. Terry
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Patent number: 9928128Abstract: A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.Type: GrantFiled: April 1, 2016Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Niels Fricke, Dung Q. Nguyen, David R. Terry
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Patent number: 9846614Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.Type: GrantFiled: June 3, 2016Date of Patent: December 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian D. Barrick, James W. Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra, Dung Q. Nguyen, David R. Terry
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Publication number: 20170351568Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: Brian D. BARRICK, James W. BISHOP, Maarten J. BOERSMA, Marcy E. BYERS, Sundeep CHADHA, Jentje LEENSTRA, Dung Q. NGUYEN, David R. TERRY
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Publication number: 20170286183Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: BRIAN D. BARRICK, JAMES W. BISHOP, MARCY E. BYERS, SUNDEEP CHADHA, CLIFF KUCHARSKI, DUNG Q. NGUYEN, DAVID R. TERRY, JING ZHANG
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Publication number: 20170286202Abstract: A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: BRIAN D. BARRICK, JAMES W. BISHOP, MARCY E. BYERS, SUNDEEP CHADHA, NIELS FRICKE, DUNG Q. NGUYEN, DAVID R. TERRY
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Publication number: 20170262281Abstract: Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Inventors: JAMES W. BISHOP, MARCY E. BYERS, STEVEN R. CARLOUGH, PAUL M. KENNEDY, ALBERT J. VAN NORSTRAND, JR., PHILLIP G. WILLIAMS
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Patent number: 8914538Abstract: A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval.Type: GrantFiled: May 13, 2010Date of Patent: December 16, 2014Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Marcy E. Byers, Kenneth M. Valk
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Patent number: 8479261Abstract: A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip.Type: GrantFiled: May 13, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Marcy E. Byers, William T. Flynn, Kenneth M. Valk
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Publication number: 20110283028Abstract: A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval.Type: ApplicationFiled: May 13, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcy E. Byers, Kenneth M. Valk
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Publication number: 20110283029Abstract: A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip.Type: ApplicationFiled: May 13, 2010Publication date: November 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marcy E. Byers, William T. Flynn, Kenneth M. Valk