Patents by Inventor Marek Kostrzewa

Marek Kostrzewa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8809964
    Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 19, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: François Andrieu, Emmanuel Augendre, Laurent Clavelier, Marek Kostrzewa
  • Publication number: 20110233732
    Abstract: A substrate configured to support at least one electronic or electromechanical component and one or more nano-elements, formed with a base support, with a catalytic system, with a barrier layer, and with a layer configured to receive the electronic or electromechanical component, in single-crystal Si or in Ge or in a mixture of these materials. The catalytic system lies on the base support without any contact with the layer configured to receive electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer configured to receive the electronic or electromechanical component. This barrier layer is without any contact with the base support.
    Type: Application
    Filed: August 31, 2009
    Publication date: September 29, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Thomas Goislard De Monsabert, Chrystel Deguet, Jean Dijon, Marek Kostrzewa
  • Patent number: 7951659
    Abstract: A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 31, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Younes Lamrani, Jean-Charles Barbe, Marek Kostrzewa
  • Patent number: 7947564
    Abstract: A method of fabricating a mixed microtechnology structure includes providing a provisional substrate including a sacrificial layer on which is formed a mixed layer including at least first patterns of a first material and second patterns of a second material different from the first material, where the first and second patterns reside adjacent the sacrificial layer. The sacrificial layer is removed exposing a mixed surface of the mixed layer, the mixed surface including portions of the first patterns and portions of the second patterns. A continuous is formed covering layer of a third material on the mixed surface by direct bonding.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 24, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Marek Kostrzewa, Hubert Moriceau, Marc Zussy
  • Patent number: 7879690
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 1, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Publication number: 20110001184
    Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
    Type: Application
    Filed: February 11, 2009
    Publication date: January 6, 2011
    Inventors: Francois Andrieu, Emmanuel Augendre, Laurent Clavelier, Marek Kostrzewa
  • Publication number: 20100041205
    Abstract: A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.
    Type: Application
    Filed: July 17, 2009
    Publication date: February 18, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Younes LAMRANI, Jean-Charles Barbe, Marek Kostrzewa
  • Publication number: 20090246946
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Publication number: 20080311725
    Abstract: A method for assembling by molecular bonding two substrates, at least one of which is made of a semiconductor material characterised in that one of substrates, called a first substrate, includes a surface (A), where at least one portion is flat and provided with an initial surface roughness compatible with the molecular bonding. The inventive method consists in depositing a thin oxide or nitride bonding layer, whose thickness ranges from 10 to 20 nm, on at least one portion of the surface flat part of the first substrate for carrying out a molecular bonding without pre-polishing, in saturating the thin bonding layer with hydroxyl groups, in bringing the thin bonding layer saturated with hydroxyl groups in contact with the second substrate (10) surface (B) which is at least locally flat with respect to the flat part of the surface (A) and saturated with hydroxyl groups and in carrying out a hydrophilic molecular bonding between said two substrates.
    Type: Application
    Filed: July 5, 2006
    Publication date: December 18, 2008
    Inventors: Lea Di Cioccio, Marek Kostrzewa, Marc Zussy
  • Patent number: 7422958
    Abstract: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 9, 2008
    Assignees: S.O.I.Tec Silicon on Insulator Technologies, Commissariat a l'Energie Atomique
    Inventors: Marek Kostrzewa, Fabrice Letertre
  • Publication number: 20080153251
    Abstract: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.
    Type: Application
    Filed: June 21, 2007
    Publication date: June 26, 2008
    Inventors: MAREK KOSTRZEWA, Fabrice Letertre
  • Publication number: 20080079123
    Abstract: A method of fabricating a mixed microtechnology structure includes providing a provisional substrate including a sacrificial layer on which is formed a mixed layer including at least first patterns of a first material and second patterns of a second material different from the first material, where the first and second patterns reside adjacent the sacrificial layer. The sacrificial layer is removed exposing a mixed surface of the mixed layer, the mixed surface including portions of the first patterns and portions of the second patterns. A continuous is formed covering layer of a third material on the mixed surface by direct bonding.
    Type: Application
    Filed: September 18, 2007
    Publication date: April 3, 2008
    Inventors: Marek Kostrzewa, Hubert Moriceau, Marc Zussy
  • Publication number: 20080020547
    Abstract: The invention concerns a method for transferring at least one object of micrometric or millimetric size onto a host substrate by means of a handle. The method comprises the following steps: fixing a polymer handle on said object in order to be able to obtain a structure, constituted of the handle and the object superimposed, and deformable, surface preparation of the face of the object opposite the handle with a view to its adhesion on a face of the host substrate, bringing into contact and adhesion of said face of the object on said face of the host substrate after deformation of at least the handle, removal of the polymer handle.
    Type: Application
    Filed: October 18, 2005
    Publication date: January 24, 2008
    Inventors: Marek Kostrzewa, Lea Di Cioccio, Marc Zussy
  • Publication number: 20080009123
    Abstract: A method for bonding two free surfaces, respectively of first and second different substrates, includes a formation step, on the free surface of the first substrate, of a self-assembled mono-molecular layer consisting of a thiol compound of the SH—R—X type, where —R is a carbonaceous chain and —X is a group selected from the group consisting in —H, —OH and —COOH, at least said free surface of the first substrate being formed by a material able to form molecular bonds with the —SH group of the thiol compound. The method also includes preparing the free surface of the second substrate consisting in saturating the free surface of the second substrate with —H groups if —X is a —H group or with —OH groups if —X is selected from the group consisting in —OH and —COOH, and placing the two free surfaces in contact.
    Type: Application
    Filed: December 6, 2005
    Publication date: January 10, 2008
    Applicant: Commissariat A Lenergie Atomique
    Inventors: Marek Kostrzewa, Lea Di Cioccio, Guillaume Delapierre