Patent number: 9804206
Abstract: A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses predetermined voltage thresholds (VA, VB, VC, VD), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (SA, SB, SC, SD), the number of the interim signals corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); providing an FPGA system (10) comprising differential buffers (11 A, 11 B, 11 C, 11 D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); inputting, to an input of each differential buffer (11 A, 11 B, 11 C, 11 D), one interim signal (SA, SB, SC, SD) and a reference voltage corresponding to a particular preset voltage threshold (VA, VB, VC, VD); reading, by means of vector generators (31 A, 31 B, 31 C, 31 D), assigned separately to each of the sequences
Type:
Grant
Filed:
August 29, 2014
Date of Patent:
October 31, 2017
Assignee:
UNIWERSYTET JAGIELLONSKI
Inventors:
Marek Palka, Pawel Moskal
Publication number: 20160209449
Abstract: A method for measuring parameters of an analog signal to determine times at which the analog signal (S) crosses pre-determined voltage thresholds (VA, VB, VC, VD), the method comprising the steps of: splitting the analog signal (S) into a number of interim signals (SA, SB, SC, SD), the number of the interim signals corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); providing an FPGA system (10) comprising differential buffers (11A, 11B, 11C, 11D) with outputs connected to a number of sequences (20A, 20B, 20C, 20D) of delay elements (21, 22, 23), the number of sequences of delay elements corresponding to the number of the preset voltage thresholds (VA, VB, VC, VD); inputting, to an input of each differential buffer (11A, 11B, 11C, 11D), one interim signal (SA, SB, SC, SD) and a reference voltage corresponding to a particular preset voltage threshold (VA, VB, VC, VD); reading, by means of vector generators (31A, 31B, 31C, 31D), assigned separately to each of the sequences (20A, 20B,
Type:
Application
Filed:
August 29, 2014
Publication date:
July 21, 2016
Applicant:
Uniwersytet Jagiellonski
Inventors:
Marek PALKA, Pawel MOSKAL