Abstract: An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.

Abstract: Methods for forming field emission and/or field ionization structures with self-aligned gate electrode structures involve forming a cavity in a first face of a substrate and forming an oxide layer in the cavity. The oxide layer forms a mold for making a sharp field emission tip which will be exposed on a second face of the substrate. In a first method a gate electrode is formed in the substrate. The gate electrode is automatically spaced apart from and insulated from the tip by the oxide layer. The gate electrode may comprise a doped region in the substrate. In a variant method, a gate electrode is formed in a thin metal film deposited on the second face of the substrate. A photoresist mask is created by shining ultraviolet light on the first face of the substrate to expose the underside of a layer of photoresist deposited on the metal film in an area adjacent the tip mold. The mask is automatically aligned with the tip mold.

Abstract: An electrostatic discharge circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first CMOS inverter comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the source of the second NMOS FET connected to Vss, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.