Abstract: A method for low latency access to the control space. A pipeline processor executes instructions in multiple stages including a decode stage, one or more execution, stages, and a writeback stage. A control space access instruction includes a first field containing a control register specifier and a second field containing a general purpose register specifier. The decode stage is configured to decode the first and second fields and place the decoded contents on a global operand bus. The specified control register is addressed from the global operand bus while the access instruction is in decode. In the case of a read instruction, the addressed control register places its contents on the global operand bus while the instruction remains in decode.

Abstract: A processor having an execution pipeline and a cache memory including a plurality of cache blocks with instruction words held in selected ones of the cache blocks. An ICBI address buffer is provided for holding addresses of instruction cache blocks to be invalidated by ICBI instructions pending in the processor's execution pipeline. An instruction cache controller coupled to the cache memory generates cache accesses to invalidate specified cache blocks in response to receiving buffered addresses from the ICBI address buffer. Preferably the cache accesses serve to commit ICBI instructions to the instruction cache asynchronously with respect to the processor's execution pipeline.

Abstract: A data processing system including a memory system and a plurality of peripheral components. A processor is coupled to the memory and peripheral components. A plurality of pipeline stages are implemented within the processor where each stage is configured to perform specific operations according to instructions then associated with that stage. A snapshot register is associated with at least some of the pipeline stages where the snapshot register configured to store data describing the state of execution of the instruction then associated with that stage.