Patents by Inventor Margaret Huang

Margaret Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11614514
    Abstract: For example, an apparatus may include a radar, the radar may include a reconfigurable radio configured, based on a plurality of reconfigurable radio parameters, to transmit a plurality of Transmit (Tx) radar signals via a plurality of Tx antennas, to receive via a plurality of Receive (Rx) antennas a plurality of Rx radar signals based on the plurality of Tx radar signals, and to provide digital radar samples based on the Rx radar signals; a radar perception processor configured to generate radar perception data based on the digital radar samples, the radar perception data representing semantic information of an environment of the radar; and a feedback controller to configure the plurality of reconfigurable radio parameters based on the radar perception data, and to feedback the reconfigurable radio parameters to the reconfigurable radio.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 28, 2023
    Assignee: INTEL CORPORATION
    Inventors: Chulong Chen, Pradyumna S. Singh, Saiveena Kesaraju, Shengbo Xu, Wenling Margaret Huang, Ophir Shabtay
  • Publication number: 20220196798
    Abstract: According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.
    Type: Application
    Filed: July 14, 2021
    Publication date: June 23, 2022
    Inventors: Chulong CHEN, Wenling Margaret HUANG, Saiveena KESARAJU, Ivan SIMÕES GASPAR, Pradyumna S. SINGH, Biji GEORGE, Dipan Kumar MANDAL, Om Ji OMER, Sreenivas SUBRAMONEY, Yuval AMIZUR, Leor BANIN, Hao CHEN, Nir DVORECKI, Shengbo XU
  • Publication number: 20210229281
    Abstract: Various aspects of methods, systems, and use cases include techniques for training or using a model to control a robot. A method may include identifying a set of action primitives applicable to a set of robots, receiving information corresponding to a task (e.g., a collaborative task), and determining at least one action primitive based on the received information. The method may include training a model to control operations of at least one robot of the set of robots using the received information and the at least one action primitive.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 29, 2021
    Inventors: Venkat Natarajan, Arjun Kg, Gagan Acharya, Amit Sudhir Baxi, Rita H. Wouhaybi, Wen-Ling Margaret Huang
  • Patent number: 10802680
    Abstract: Techniques are disclosed for generating a pixel-aligned layout grid. In some examples, a method may include receiving an input that quantifies a selected one of multiple horizontal dimensions, a number of columns, a column width, a gutter width, and a margin width, of a layout grid. The method may also include, responsive to receiving the input, calculating respective integer values for the remaining multiple horizontal dimensions based on the received input quantifying the selected one of the multiple horizontal dimensions. The method may further include generating a layout grid based on the integer values for the remaining multiple horizontal dimensions and the received input quantifying the selected one of the multiple horizontal dimensions, and rendering the generated layout grid as a pixel-aligned layout grid.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 13, 2020
    Assignee: Adobe Inc.
    Inventors: Randall James Edmunds, Christopher R. Bank, Ashley Margaret Huang
  • Publication number: 20200225317
    Abstract: For example, an apparatus may include a radar, the radar may include a reconfigurable radio configured, based on a plurality of reconfigurable radio parameters, to transmit a plurality of Transmit (Tx) radar signals via a plurality of Tx antennas, to receive via a plurality of Receive (Rx) antennas a plurality of Rx radar signals based on the plurality of Tx radar signals, and to provide digital radar samples based on the Rx radar signals; a radar perception processor configured to generate radar perception data based on the digital radar samples, the radar perception data representing semantic information of an environment of the radar; and a feedback controller to configure the plurality of reconfigurable radio parameters based on the radar perception data, and to feedback the reconfigurable radio parameters to the reconfigurable radio.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Chulong Chen, Pradyumna S. Singh, Saiveena Kesaraju, Shengbo Xu, Wenling Margaret Huang, Ophir Shabtay
  • Publication number: 20190354247
    Abstract: Techniques are disclosed for generating a pixel-aligned layout grid. In some examples, a method may include receiving an input that quantifies a selected one of multiple horizontal dimensions, a number of columns, a column width, a gutter width, and a margin width, of a layout grid. The method may also include, responsive to receiving the input, calculating respective integer values for the remaining multiple horizontal dimensions based on the received input quantifying the selected one of the multiple horizontal dimensions. The method may further include generating a layout grid based on the integer values for the remaining multiple horizontal dimensions and the received input quantifying the selected one of the multiple horizontal dimensions, and rendering the generated layout grid as a pixel-aligned layout grid.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Applicant: Adobe Inc.
    Inventors: Randall James Edmunds, Christopher R. Bank, Ashley Margaret Huang
  • Patent number: 7762017
    Abstract: A customizable envelope formed from interchangeable components allows the user to create various color and texture arrangements. The envelope is formed using two separate pieces of paper or other similar sheet material, each of which includes two foldable end flaps and a central portion. Both sheets are generally rectangular in shape and, when assembled to form the finished envelope, are preferably oriented so that their elongate axes are at a 90° angle to each other. In one form, the central portion of one sheet has a pair of elongated slits preferably formed parallel to the longitudinal axis of the sheet and located near the top and bottom edges, respectively. The second sheet is sized so that it will be received in these slits. After assembly, the portion of the first, slitted sheet, exterior to the slits appears to frame the central portion of the second sheet, providing a framed opening on either the inner or outer surface of the completed envelope.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 27, 2010
    Assignee: M. & Co., Inc.
    Inventor: Margaret Huang
  • Publication number: 20080078816
    Abstract: A customizable envelope formed from interchangeable components allows the user to create various color and texture arrangements. The envelope is formed using two separate pieces of paper or other similar sheet material, each of which includes two foldable end flaps and a central portion. Both sheets are generally rectangular in shape and, when assembled to form the finished envelope, are preferably oriented so that their elongate axes are at a 90° angle to each other. In one form, the central portion of one sheet has a pair of elongated slits preferably formed parallel to the longitudinal axis of the sheet and located near the top and bottom edges, respectively. The second sheet is sized so that it will be received in these slits. After assembly, the portion of the first, slitted sheet, exterior to the slits appears to frame the central portion of the second sheet, providing a framed opening on either the inner or outer surface of the completed envelope.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: M. & Co., Inc.
    Inventor: Margaret Huang
  • Patent number: 5920093
    Abstract: A semiconductor device (120) is formed in a silicon-on-insulator (SOI) substrate (135). The semiconductor device (120) has a channel region (126) that is controlled by a gate structure (129). The channel region (126) has a doping profile that is essentially uniform where the channel region (126) is under the gate structure (129). This eliminates the parasitic channel region that is common with conventional field effect transistors (FETs) that are formed in SOI substrates. Consequently, the semiconductor device (120) of the present invention does not suffer from the "kink" problem that is common to conventional FET devices.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: July 6, 1999
    Assignee: Motorola, Inc.
    Inventors: Wen Ling Margaret Huang, Ying-Che Tseng
  • Patent number: 5780352
    Abstract: A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: July 14, 1998
    Assignee: Motorola, Inc.
    Inventors: Heemyong Park, Wen-Ling Margaret Huang, Juergen Foerstner, Marco Racanelli
  • Patent number: 5670389
    Abstract: A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: September 23, 1997
    Assignee: Motorola, Inc.
    Inventors: Wen-Ling Margaret Huang, Hyungcheol Shin, Marco Racanelli