Patents by Inventor Margaret L. Gibson

Margaret L. Gibson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6899785
    Abstract: Undesirable reactions (such as formation of volatile compounds or complexes) are recognized to occur during production processes (such as etching with fluorine) at interior surfaces of a reactor chamber (such as a silicon-based reactor chamber). These undesirable reactions may be minimized and controlled by priming the chamber surface by incorporating seasoning atoms and/or molecules.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kellie L. Dutra, Margaret L. Gibson, Ronald G. Meunier, Jason W. Silbergleit
  • Patent number: 6818992
    Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Douglas S. Armbrust, Margaret L. Gibson, Laura Serianni, Eric J. White
  • Patent number: 6780720
    Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: August 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jay S. Burnham, Anthony I. Chou, Toshiharu Furukawa, Margaret L. Gibson, James S. Nakos, Steven M. Shank
  • Publication number: 20040002226
    Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 1, 2004
    Applicant: International Business Machines Corporation
    Inventors: Jay S. Burnham, Anthony I. Chou, Toshiharu Furukawa, Margaret L. Gibson, James S. Nakos, Steven M. Shank
  • Publication number: 20030092272
    Abstract: Undesirable reactions (such as formation of volatile compounds or complexes) are recognized to occur during production processes (such as etching with fluorine) at interior surfaces of a reactor chamber (such as a silicon-based reactor chamber). These undesirable reactions may be minimized and controlled by priming the chamber surface by incorporating seasoning atoms and/or molecules.
    Type: Application
    Filed: November 5, 2001
    Publication date: May 15, 2003
    Inventors: Kellie L. Dutra, Margaret L. Gibson, Ronald G. Meunier, Jason W. Silbergleit
  • Patent number: 6251775
    Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Douglas S. Armbrust, Margaret L. Gibson, Laura Serianni, Eric J. White