Patents by Inventor Margaret R. Simmons-Matthews

Margaret R. Simmons-Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked IC Devices Comprising a Workpiece Solder Connected to the TSV
    Publication number: 20130099384
    Abstract: A stacked integrated circuit (IC) device with at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
    Type: Application
    Filed: April 10, 2012
    Publication date: April 25, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Margaret R. Simmons-Matthews, Donald C. Abbott
  • IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
    Patent number: 8227295
    Abstract: A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: July 24, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Margaret R. Simmons-Matthews, Donald C. Abbott
  • METHODS FOR CONTROLLING WAFER AND PACKAGE WARPAGE DURING ASSEMBLY OF VERY THIN DIE
    Publication number: 20100190294
    Abstract: Various exemplary embodiments provide materials and methods for flip-chip packaging a thin TSV semiconductor die, which uses other packaging components, for example, a second die, as a packaging carrier to attach the thin TSV semiconductor die to a package substrate. Warpage and mis-alignment can be reduced or eliminated during the packaging process of the thin TSV die.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 29, 2010
    Inventor: Margaret R. Simmons-Matthews
  • IC DIE HAVING TSV AND WAFER LEVEL UNDERFILL AND STACKED IC DEVICES COMPRISING A WORKPIECE SOLDER CONNECTED TO THE TSV
    Publication number: 20100096738
    Abstract: A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
    Type: Application
    Filed: April 1, 2009
    Publication date: April 22, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Margaret R. Simmons-Matthews, Donald C. Abbott