Patents by Inventor Margaret Rose Simmons-Matthews
Margaret Rose Simmons-Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140183719Abstract: An electronic assembly includes a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. A plurality of first die having a thickness having their topside contacts attached to topside substrate pads on a top surface of said package substrate.Type: ApplicationFiled: March 10, 2014Publication date: July 3, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Margaret Rose Simmons-Matthews
-
Patent number: 8597978Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.Type: GrantFiled: May 17, 2012Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
-
Patent number: 8526186Abstract: An electronic assembly includes a workpiece, a through substrate via (TSV) die including a substrate and a plurality of TSVs, a topside and a bottomside having TSV connectors thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader having an inner open window is on the bottomside of the TSV die. Bonding features are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top of the heat spreader that allows a top die to be bonded thereto.Type: GrantFiled: July 11, 2011Date of Patent: September 3, 2013Assignee: Texas Instruments IncorporatedInventors: Satoshi Yokoya, Margaret Rose Simmons-Matthews
-
Publication number: 20130082407Abstract: A method of making integrated circuit package assemblies including encapsulating a plurality of dies in an encapsulation layer having an exterior surface and attaching a heat sink strip to the exterior surface of the encapsulation layer. An integrated circuit package assembly and an intermediate product used in making an integrated circuit package assembly are also disclosed.Type: ApplicationFiled: October 4, 2011Publication date: April 4, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Donald C. Abbott, Margaret Rose Simmons-Matthews
-
Publication number: 20130016477Abstract: An electronic assembly includes a workpiece, a through substrate via (TSV) die including a substrate and a plurality of TSVs, a topside and a bottomside having TSV connectors thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader having an inner open window is on the bottomside of the TSV die. Bonding features are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top of the heat spreader that allows a top die to be bonded thereto.Type: ApplicationFiled: July 11, 2011Publication date: January 17, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Satoshi Yokoya, Margaret Rose Simmons-Matthews
-
Patent number: 8313982Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.Type: GrantFiled: September 20, 2010Date of Patent: November 20, 2012Assignee: Texas Instruments IncorporatedInventors: Rajiv Dunne, Margaret Rose Simmons-Matthews
-
Patent number: 8288849Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.Type: GrantFiled: May 7, 2010Date of Patent: October 16, 2012Assignee: Texas Instruments IncorporatedInventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
-
Publication number: 20120225523Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.Type: ApplicationFiled: May 17, 2012Publication date: September 6, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
-
Publication number: 20120070939Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.Type: ApplicationFiled: September 20, 2010Publication date: March 22, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajiv Dunne, Margaret Rose Simmons-Matthews
-
Patent number: 8097964Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.Type: GrantFiled: December 29, 2009Date of Patent: January 17, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Rose Simmons-Matthews, Masazumi Amagai
-
Publication number: 20110272814Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.Type: ApplicationFiled: May 7, 2010Publication date: November 10, 2011Inventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
-
Publication number: 20110266693Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Margaret Rose Simmons-Matthews
-
Publication number: 20100171226Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.Type: ApplicationFiled: December 29, 2009Publication date: July 8, 2010Applicant: TEXAS INSTRUMENTS, INC.Inventors: Jeffrey Alan West, Margaret Rose Simmons-Matthews, Masazumi Amagai