Patents by Inventor Margaret Simmons-Matthews
Margaret Simmons-Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8815642Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: GrantFiled: October 4, 2013Date of Patent: August 26, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Patent number: 8759154Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.Type: GrantFiled: September 25, 2012Date of Patent: June 24, 2014Assignee: Texas Instruments IncorporatedInventor: Margaret Simmons-Matthews
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Publication number: 20140151895Abstract: A through-substrate via (TSV) die includes a substrate with a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface. A plurality of TSVs extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface and include an inner metal core of electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSVs. A tip deformation protecting layer of inorganic dielectric material is on the bottom side surface lateral to the TSV tips. An elastic modulus of the inorganic dielectric material is greater than (>) an elastic modulus of the electrically conductive filler material. A second dielectric layer including a polymer is on the tip deformation protecting layer.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: JEFFREY ALAN WEST, RAJESH TIWARI, MARGARET SIMMONS-MATTHEWS
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Publication number: 20140124900Abstract: A through-substrate via (TSV) die includes a substrate having a top side semiconductor surface having active circuitry therein including a plurality of transistors functionally connected and a bottom side surface, wherein the layers on the top side semiconductor surface exert a net tensile stress to the top side semiconductor surface. A plurality of TSVs which extend from the top side semiconductor surface to TSV tips which protrude from the bottom side surface include an inner metal core surrounded by a dielectric liner that forms an outer edge for the TSVs. A dielectric stack is on the bottom side surface lateral to the TSV tips including a compressive dielectric layer and a tensile dielectric layer on the compressive dielectric layer.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: JEFFREY ALAN WEST, MARGARET SIMMONS-MATTHEWS, RAJESH TIWARI
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Publication number: 20140038359Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Patent number: 8575758Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: GrantFiled: August 4, 2011Date of Patent: November 5, 2013Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Patent number: 8471577Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.Type: GrantFiled: June 11, 2010Date of Patent: June 25, 2013Assignee: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Margaret Simmons-Matthews, Jeff West
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Publication number: 20130032946Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: JEFFREY ALAN WEST, MARGARET SIMMONS-MATTHEWS, RAYMUNDO M. CAMENFORTE
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Patent number: 8344749Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.Type: GrantFiled: June 7, 2010Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Kenneth M. Butler, Margaret Simmons-Matthews
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Patent number: 8344493Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.Type: GrantFiled: January 6, 2011Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Jeffrey E. Brighton, Margaret Simmons-Matthews
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Patent number: 8298863Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.Type: GrantFiled: April 29, 2010Date of Patent: October 30, 2012Assignee: Texas Instruments IncorporatedInventor: Margaret Simmons-Matthews
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Publication number: 20120175774Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Alan West, Jeffrey E. Brighton, Margaret Simmons-Matthews
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Publication number: 20110304349Abstract: A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.Type: ApplicationFiled: June 11, 2010Publication date: December 15, 2011Applicant: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Margaret Simmons-Matthews, Jeff West
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Publication number: 20110298488Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.Type: ApplicationFiled: June 7, 2010Publication date: December 8, 2011Applicant: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Kenneth M. Butler, Margaret Simmons-Matthews
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Publication number: 20050266661Abstract: A semiconductor wafer (10) and associated methods are disclosed in which a plurality of semiconductor dice (14) include a semiconductor substrate (12) overlain by a plurality of upper layers (13) are provided with encompassing scribe streets (20) at the top surface (16) of the wafer (10) defined by inactive areas (18) between and circumscribing the dice (14). Ditches (22) in the scribe streets (20) extend from the top surface (16) to the substrate (12) for facilitating saw singulation of the dice (14).Type: ApplicationFiled: May 26, 2004Publication date: December 1, 2005Inventors: Lei Li, Vish Sundararaman, Margaret Simmons-Matthews
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Patent number: 6768212Abstract: A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.Type: GrantFiled: January 15, 2003Date of Patent: July 27, 2004Assignee: Texas Instruments IncorporatedInventors: Akira Karashima, Margaret Simmons-Matthews, Sohichi Kadoguchi
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Publication number: 20030137033Abstract: A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.Type: ApplicationFiled: January 15, 2003Publication date: July 24, 2003Inventors: Akira Karashima, Margaret Simmons-Matthews, Sohichi Kadoguchi
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Publication number: 20030090558Abstract: A molded body (20) of a printhead chip package (70) for use in a hand-held apparatus is provided. The molded body (20) has a bottom surface (22) adapted to be attached to the hand-held apparatus. A fluid reservoir (24) is formed in a central region of the molded body (20), and is bounded on its sides (26) by the molded body (20). A bottom (28) of the fluid reservoir (24) is at least partially open. A recessed cavity (30) is formed in the central region of the molded body (20) above the fluid reservoir (24), and is bounded on its sides (32) by the molded body (20). A top (34) of the recessed cavity (30) is at least partially open. A first part of a bottom (36) of the recessed cavity (30) is bounded by the molded body (20). A second part of the bottom of the recessed cavity (30) is open to a top opening (40) of the fluid reservoir (24). The recessed cavity (30) is adapted to receive a printhead chip (72) therein.Type: ApplicationFiled: March 22, 2002Publication date: May 15, 2003Inventors: Anthony L. Coyle, Margaret Simmons-Matthews