Patents by Inventor Mari Nozoe
Mari Nozoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20030204826Abstract: Secondary electrons and back scattered electrons generated by irradiating a wafer to be inspected such as a semiconductor wafer with a charged particle beam are detected by a detector. A signal proportional to the number of detected electrons is generated, and an inspection image is formed on the basis of the signal. On the other hand, in consideration of a current value and irradiation energy of a charged particle beam, an electric field on the surface of the inspection wafer, emission efficiency of the secondary electrons and back scattered electrons, and the like, an electric resistance and an electric capacity are determined so as to coincide with those in the inspection image. In a state where a difference between a resistance value in a normal portion and a resistance value in a defective portion is sufficiently increased by using the charging generated by the irradiation of electron beams, an inspection is conducted to thereby detect a defect.Type: ApplicationFiled: April 21, 2003Publication date: October 30, 2003Applicant: Hitachi, Ltd.Inventors: Hidetoshi Nishiyama, Mari Nozoe, Hiroyuki Shinada
-
Publication number: 20030201391Abstract: A circuit pattern inspecting instrument includes an electron-optical system for irradiating an electron beam on a sample, an electron beam deflector, a detector for detecting secondary charged particles from the sample, and a mode setting unit for switching between a first mode and a second mode. An electron beam current is larger in the first mode than in the second mode, and an electron beam scanning speed is higher in the first mode than in the second mode. The circuit pattern inspecting instrument is configured so that first the sample is observed in the first mode, then a particular position on the sample is selected based on image data produced by an output of the detector in the first mode, and then the particular position on the sample is observed in the second mode.Type: ApplicationFiled: April 2, 2003Publication date: October 30, 2003Inventors: Hiroyuki Shinada, Atsuko Takafuji, Takanori Ninomiya, Yuko Sasaki, Mari Nozoe, Hisaya Murakoshi, Taku Ninomiya, Yuji Kasai, Hiroshi Makino, Yutaka Kaneko, Kenji Tanimoto
-
Publication number: 20030179007Abstract: Electron beam is irradiated to a wafer in the midst of steps at predetermined intervals by a plurality of times under a condition in which a junction becomes rearward bias and a difference in characteristic of a time period of alleviating charge in the rearward bias is monitored. As a result, charge is alleviated at a location where junction leakage is caused in a time period shorter than that of a normal portion and therefore, a potential difference is produced between the normal portion and a failed portion and is observed in a potential contrast image as a difference in brightness. By consecutively repeating operation of acquiring the image, executing an image processing in real time and storing a position and brightness of the failed portion, the automatic inspection of a designated region can be executed. Information of image, brightness and distribution of the failed portion is preserved and outputted automatically after inspection.Type: ApplicationFiled: March 25, 2003Publication date: September 25, 2003Applicant: Hitachi, LtdInventors: Mari Nozoe, Mitsuo Suga, Yoichiro Neo, Hidetoshi Nishiyama
-
Publication number: 20030169060Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is radiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: ApplicationFiled: March 6, 2003Publication date: September 11, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
-
Patent number: 6618850Abstract: Secondary electrons and back scattered electrons generated by irradiating a wafer to be inspected, such as a semiconductor wafer, with a charged particle beam are detected by a detector. A signal proportional to the number of detected electrons is generated, and an inspection image is formed on the basis of this signal. On the other hand, in consideration of a current value and irradiation energy of a charged particle beam, an electric field on the surface of the inspection wafer, emission efficiency of the secondary electrons and back scattered electrons, and the like, an electric resistance and an electric capacitance are determined so as to coincide with those in the inspection image. In a state where a difference between a resistance value in a normal portion and a resistance value in a defective portion is sufficiently increased by using the charging generated by the irradiation of electron beams, an inspection is thereby conducted to detect a defect.Type: GrantFiled: February 20, 2001Date of Patent: September 9, 2003Assignee: Hitachi, Ltd.Inventors: Hidetoshi Nishiyama, Mari Nozoe, Hiroyuki Shinada
-
Publication number: 20030164460Abstract: An electron beam (area beam) having a fixed area is irradiated onto the surface of a semiconductor sample, and reflected electrons from the sample surface are imaged by the imaging lens, and images of a plurality of regions of the surface of the semiconductor sample are obtained and stored in the image storage unit, and the stored images of the plurality of regions are compared with each other, and the existence of a defect in the regions and the defect position are measured. By doing this, in an apparatus for testing a pattern defect of the same design, foreign substances, and residuals on a wafer in the manufacturing process of a semiconductor apparatus by an electron beam, speeding-up of the test can be realized.Type: ApplicationFiled: March 28, 2003Publication date: September 4, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Yusuke Yajima, Hisaya Murakoshi, Masaki Hasegawa, Mari Nozoe, Atsuko Takafuji, Katsuya Sugiyama, Katsuhiro Kuroda, Kaoru Umemura, Yasutsugu Usami
-
Patent number: 6613593Abstract: A method and apparatus for inspecting a semiconductor device in which failure occurrence conditions on a whole wafer are estimated by calculating the statistic of potential contrasts in pattern sections from sampled images to implement higher throughput, and defective conditions of a process are detected at an early stage with the help of time series data of the estimated result.Type: GrantFiled: August 31, 2001Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Maki Tanaka, Masahiro Watanabe, Kenji Watanabe, Mari Nozoe, Hiroshi Miyai
-
Publication number: 20030130806Abstract: A process management system in accordance with the present invention includes inspection apparatuses for inspecting defects on a wafer, the inspection apparatuses being connected through a communication network, inspection information and image information obtained from these inspection apparatuses being collected to construct a data base and an image file, therein definition of defects is given by combinations of elements which characterize the defect based on the inspection information and the image information obtained from the inspection apparatuses. By giving definition of the defect, characteristics of the defect can be subdivided and known. Therefore, the cause of a defect can be studied.Type: ApplicationFiled: January 16, 2003Publication date: July 10, 2003Applicant: Hitachi, Ltd.Inventors: Fumio Mizuno, Seiji Isogai, Kenji Watanabe, Yasuhiro Yoshitake, Terushige Asakawa, Yuichi Ohyama, Hidekuni Sugimoto, Seiji Ishikawa, Masataka Shiba, Jun Nakazato, Makoto Ariga, Tetsuji Yokouchi, Toshimitsu Hamada, Ikuo Suzuki, Masami Ikota, Mari Nozoe, Isao Miyazaki, Yoshiharu Shigyo
-
Patent number: 6586952Abstract: Electron beam is irradiated to a wafer in the midst of steps at predetermined intervals by a plurality of times under a condition in which a junction becomes rearward bias and a difference in characteristic of a time period of alleviating charge in the rearward bias is monitored. As a result, charge is alleviated at a location where junction leakage is caused in a time period shorter than that of a normal portion and therefore, a potential difference is produced between the normal portion and a failed portion and is observed in a potential contrast image as a difference in brightness. By consecutively repeating operation of acquiring the image, executing an image processing in real time and storing a position and brightness of the failed portion, the automatic inspection of a designated region can be executed. Information of image, brightness and distribution of the failed portion is preserved and outputted automatically after inspection.Type: GrantFiled: June 15, 2001Date of Patent: July 1, 2003Inventors: Mari Nozoe, Mitsuo Suga, Yoichiro Neo, Hidetoshi Nishiyama
-
Patent number: 6583414Abstract: There are provided an inline inspection system and inspection method for inspecting the substrate surface on which semiconductors and circuit patterns are formed by radiating thereto white beam, laser beam or electron beam, and reviewing, inspecting and discriminating the detected roughness and figure defect, particle and moreover electrical defect on the surface with higher accuracy within a short period of time with the same instrument. Thereby, automatic movement to the position to be reviewed, acquisition of image and classification can be realized. On the occasion of identifying the position to be reviewed on a sample and forming an image through irradiation of electron beam on the basis of the positional information of defect detected with the other inspection instrument, an electrical defect can be reviewed with the voltage contrast mode by designating the electron beam irradiation condition, detectors and detecting condition depending on a kind of defect to be reviewed.Type: GrantFiled: November 30, 2000Date of Patent: June 24, 2003Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.Inventors: Mari Nozoe, Hidetoshi Nishiyama, Shigeaki Hijikata, Kenji Watanabe, Koji Abe
-
Patent number: 6583634Abstract: In order to obtain optimum irradiation conditions of an electron beam according to the material and structure of a circuit pattern to be inspected and the kind of a failure to be detected and inspect under the optimum conditions without delay of the inspection time, an inspection device for irradiating the electron beam 19 to the sample board 9 which is a sample, detecting generated secondary electrons by the detector 7, storing obtained signals sequentially in the storage, comparing the same pattern stored in the storage by the comparison calculation unit, and extracting a failure by comparing the predetermined threshold value with the comparison signal by the failure decision unit is provided, wherein the optimum value of the irradiation energy is stored in the data base inside the device beforehand according to the structure of a sample and a recommended value of the irradiation energy suited to inspection can be searched for by inputting or selecting the irradiation energy by a user or inputting informatiType: GrantFiled: April 27, 2000Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Mari Nozoe, Hiroyuki Shinada, Kenji Watanabe, Keiichi Saiki, Aritoshi Sugimoto, Hiroshi Morioka, Maki Tanaka, Hiroshi Miyai
-
Patent number: 6583413Abstract: A circuit pattern inspecting instrument includes an electron-optical system for irradiating an electron beam on a sample, an electron beam deflector, a detector for detecting secondary charged particles from the sample, and a mode setting unit for switching between a first mode and a second mode. An electron beam current is larger in the first mode than in the second mode, and an electron beam scanning speed is higher in the first mode than in the second mode. The circuit pattern inspecting instrument is configured so that first the sample is observed in the first mode, then a particular position on the sample is selected based on image data produced by an output of the detector in the first mode, and then the particular position on the sample is observed in the second mode.Type: GrantFiled: August 30, 2000Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Atsuko Takafuji, Takanori Ninomiya, Yuko Sasaki, Mari Nozoe, Hisaya Murakoshi, Taku Ninomiya, Yuji Kasai, Hiroshi Makino, Yutaka Kaneko, Kenji Tanimoto
-
Publication number: 20030094572Abstract: In a method for inspecting positions and types of defects on wafers with circuit patterns in the semiconductor manufacturing process, a highly sensitive inspection is made regardless of the types and materials of junctions of circuit patterns of the semiconductor devices, different kinds of defects being distinguished from one another. Further, extraordinary electrification of the circuit pattern is prevented and an area to be exposed to an electron beam is controlled evenly and at a desired voltage. Thus, this method contributes to the early setup of manufacturing processes of integrated circuits and early measures against defects, increasing the reliability and productivity of the semiconductor devices.Type: ApplicationFiled: June 12, 2002Publication date: May 22, 2003Applicant: Hitachi, Ltd.Inventors: Miyako Matsui, Mari Nozoe
-
Patent number: 6559663Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with: the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.Type: GrantFiled: October 25, 2001Date of Patent: May 6, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
-
Publication number: 20030071646Abstract: Provided is an inspection technique of a semiconductor device, enabling an inspection on a wafer being in a process, which cannot be carried out by a conventional technique, to be performed at an early stage, and capable of promptly grasping a problem with accuracy and taking a countermeasure on a manufacturing process immediately. A wafer being in a process is irradiated with an electron beam a plurality of times at predetermined intervals under a condition that a junction is backward biased, and secondary electron signals are monitored, thereby evaluating relax time characteristic of a backward bias potential in a pn junction. Since the potential in the pn junction decreases according to the intensity of a backward bias current in intermittent time, a backward bias current can be specified from a luminance signal of a potential contrast image.Type: ApplicationFiled: June 18, 2002Publication date: April 17, 2003Inventors: Yoichiro Neo, Mari Nozoe
-
Patent number: 6542830Abstract: A process management system in accordance with the present invention includes inspection apparatuses for inspecting defects on a wafer, the inspection apparatuses being connected through a communication network, inspection information and image information obtained from these inspection apparatuses being collected to construct a data base and an image file, therein definition of defects is given by combinations of elements which characterize the defect based on the inspection information and the image information obtained from the inspection apparatuses. By giving definition of the defect, characteristics of the defect can be subdivided and known. Therefore, the cause of a defect can be studied.Type: GrantFiled: September 10, 1998Date of Patent: April 1, 2003Assignees: Hitachi, Ltd., Hitachi Instruments Engineering Co., Ltd.Inventors: Fumio Mizuno, Seiji Isogai, Kenji Watanabe, Yasuhiro Yoshitake, Terushige Asakawa, Yuichi Ohyama, Hidekuni Sugimoto, Seiji Ishikawa, Masataka Shiba, Jun Nakazato, Makoto Ariga, Tetsuji Yokouchi, Toshimitsu Hamada, Ikuo Suzuki, Masami Ikota, Mari Nozoe, Isao Miyazaki, Yoshiharu Shigyo
-
Publication number: 20030058444Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.Type: ApplicationFiled: November 5, 2002Publication date: March 27, 2003Applicant: HITACHI, LTD.Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Kohichi Hayakawa, Maki Ito
-
Publication number: 20030057971Abstract: A semiconductor defect inspection device and method for detecting defects of partially finished substrates (semiconductor wafers) for semiconductor devices is provided. The substrate surface is irradiated with a charged particle beam and a voltage contrast image is obtained while the charged voltage is controlled at a desired level, and the electric resistances of the irradiated area from the image are calculated to detect a defect and identify the type of defect. Further, the distribution of electric resistances on the whole surface of the substrate can be quickly worked out. The charged particle beam irradiation conditions are varied in order to bring the charged voltage of the area to a desired value. With this device/method, electric resistances of small portions at desired charged voltages and the corresponding electric resistances are measured in a non-contact manner to determine the type of defect.Type: ApplicationFiled: August 1, 2002Publication date: March 27, 2003Inventors: Hidetoshi Nishiyama, Mari Nozoe
-
Patent number: 6504609Abstract: Inspection method, apparatus, and system for a circuit pattern in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.Type: GrantFiled: April 4, 2002Date of Patent: January 7, 2003Assignee: Hitachi, Ltd.Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
-
Publication number: 20020197750Abstract: A method and its apparatus for inspecting a semiconductor device in which failure occurrence conditions on a whole wafer are estimated by calculating the statistic of potential contrasts in pattern sections from sampled images to implement higher througput and defective conditions of process are detected at an early stage with the help of time series data of the estimated result.Type: ApplicationFiled: August 31, 2001Publication date: December 26, 2002Inventors: Maki Tanaka, Masahiro Watanabe, Kenji Watanabe, Mari Nozoe, Hiroshi Miyai