Abstract: A first chip includes a first insulating layer, a first device layer laminated on the first insulating layer, a first multilayer wiring layer laminated on the first device layer, and a first anchor. A high-frequency circuit is in the first chip. A second chip includes a substrate, a second multilayer wiring layer on the substrate, and a second anchor. A control circuit that controls the high-frequency circuit is in the second chip. The first anchor is embedded in the first device layer and the first insulating layer, and exposed from a surface of the first insulating layer. The second anchor is embedded in the second multilayer wiring layer, and exposed from a surface of the second multilayer wiring layer. The first and second anchors are formed from an identical metal material.

Abstract: MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5° to about 60° within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

Abstract: A semiconductor device is flip-chip mounted on a mounting substrate. A mold resin seals the semiconductor device. An insulating heat transfer member having a thermal conductivity higher than a thermal conductivity of the mold resin is on a surface of the semiconductor device facing the mounting substrate. The semiconductor device includes a device layer including a transistor, a plurality of bumps that are on a surface of the device layer facing the mounting substrate and are connected to the mounting substrate, and an insulating layer that is on a surface of the device layer opposite to the surface facing the mounting substrate. When the mounting substrate is viewed in plan view, the transistor has a non-overlapping portion that does not overlap with any of the bumps. The heat transfer member is continuous from a region overlapping with the non-overlapping portion to at least one of the bumps.

Abstract: At least one of transistors is in a device layer. A plurality of bumps are on one surface of the device layer. An insulating layer is on a surface of the device layer opposite to the surface having the plurality of bumps. The heat transfer layer is in contact with a surface of the insulating layer opposite to a surface on which the device layer is disposed. The heat transfer layer is formed of an insulating material having a thermal conductivity higher than a thermal conductivity of the insulating layer. When the device layer is viewed in plan view, one first transistor of the transistors includes a non-overlapping portion which is a portion not overlapping with the plurality of bumps, and the heat transfer layer is continuous from a portion overlapping with the non-overlapping portion to a portion overlapping with at least one of the plurality of bumps.

Abstract: A semiconductor element having a structure in which a wiring layer, an element formation layer, and a first insulating layer are stacked is mounted on a first surface of a module substrate in a state where the wiring layer faces the module substrate. The electronic component is mounted on the first surface of the module substrate. A resin layer is on the first surface of the module substrate. First and second recessed portions are in the resin layer, a semiconductor element is in the first recessed portion, and the electronic component is in the second recessed portion. When the first surface is set as a height reference, an upper surface of the resin layer includes a region which is higher than or equal to heights of an upper surface of the semiconductor element and an upper surface of the electronic component, around the semiconductor element and the electronic component.

Abstract: An elastic wave device includes a piezoelectric substrate mainly including lithium niobate, an interdigital transducer electrode provided on the piezoelectric substrate, and a dielectric film, provided on the piezoelectric substrate and covering the interdigital transducer electrode, and mainly including silicon oxide. The elastic wave device uses a Rayleigh wave. The interdigital transducer electrode includes main electrode layers that include one or more first main electrode layer made of a metal with a C112/C12 ratio greater than the C112/C12 ratio of the silicon oxide with regard to the elastic constants C11 and C12. The sum of the thicknesses of the one or more first main electrode layers is about 55% or more based on the thickness of the whole interdigital transducer electrode is about 100%.

Abstract: A semiconductor device includes a semiconductor substrate; at least one transistor located on the semiconductor substrate and including a plurality of semiconductor layers; an electrode provided for the transistor; an organic insulating film having an opening in a region overlapping the transistor and the electrode in plan view in a first direction perpendicular to the semiconductor substrate; and a bump located over the at least one transistor in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film. The width of the bump in a second direction parallel to the semiconductor substrate is smaller than the width of the opening of the organic insulating film in the second direction.

Abstract: A semiconductor device includes a semiconductor substrate, at least one transistor on the semiconductor substrate and including semiconductor layers, a wiring on the transistor, a first insulating film including a first opening in a region overlapping the transistor and the wiring in plan view in a first direction perpendicular to the semiconductor substrate, a first redistribution layer on the first insulating film, overlapping the at least one transistor in the first direction in plan view, and electrically connected to the wiring via the first opening, a second insulating film covering the first redistribution layer and the first insulating film and provided with a second opening in a region overlapping at least a part of the first redistribution layer in the first direction in plan view, and a bump electrically connected to the first redistribution layer via the second opening.

Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.

Abstract: A semiconductor device has a semiconductor substrate, at least one first transistor that has a mesa structure including one or more semiconductor layers, a first bump that overlaps the first transistor and extends in a first direction, and a second bump, in which the mesa structure has a first end portion on one end side in a second direction and a second end portion on the other end side in the second direction. The opening has a first opening end portion and a second opening end portion that are adjacent in the second direction. In plan view, the first opening end portion is closer to the second bump than the second opening end portion and the first end portion and the second end portion of the mesa structure are disposed between the first opening end portion and the second opening end portion.

Abstract: A semiconductor device includes a semiconductor substrate; at least one first transistor, each first transistor including a mesa structure including one or more semiconductor layers; a first bump overlapping the first transistors and extending in a first direction; and a second bump. The mesa structure includes a first end portion at one end in a second direction and a second end portion at another end in the second direction. In plan view, an outer periphery of the first bump includes a first side and a second side extending in the first direction and arranged next to each other in the second direction. The first side is closer to the second bump than the second side in the second direction. The first end portion and the second end portion of the mesa structure are between the first side and the second side.

Abstract: An elastic wave device includes a piezoelectric substrate mainly including lithium niobate, an interdigital transducer electrode provided on the piezoelectric substrate, and a dielectric film, provided on the piezoelectric substrate and covering the interdigital transducer electrode, and mainly including silicon oxide. The elastic wave device uses a Rayleigh wave. The interdigital transducer electrode includes main electrode layers that include one or more first main electrode layer made of a metal with a C112/C12 ratio greater than the C112/C12 ratio of the silicon oxide with regard to the elastic constants C11 and C12. The sum of the thicknesses of the one or more first main electrode layers is about 55% or more based on the thickness of the whole interdigital transducer electrode is about 100%.

Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.

Abstract: An elastic wave device includes a piezoelectric substrate mainly including lithium niobate, an interdigital transducer electrode provided on the piezoelectric substrate, and a dielectric film, provided on the piezoelectric substrate and covering the interdigital transducer electrode, and mainly including silicon oxide. The elastic wave device uses a Rayleigh wave. The interdigital transducer electrode includes main electrode layers that include one or more first main electrode layer made of a metal with a C112/C12 ratio greater than the C112/C12 ratio of the silicon oxide with regard to the elastic constants C11 and C12. The sum of the thicknesses of the one or more first main electrode layers is about 55% or more based on the thickness of the whole interdigital transducer electrode is about 100%.

Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.

Abstract: In an elastic wave device, an IDT electrode is provided on a piezoelectric substrate and a first silicon oxide film covers the IDT electrode. A high-acoustic-velocity dielectric film covers the first silicon oxide film. A second silicon oxide film is provided on the high-acoustic-velocity dielectric film. The piezoelectric substrate is made of lithium niobate. The high-acoustic-velocity dielectric film propagates longitudinal waves at an acoustic velocity higher than an acoustic velocity of longitudinal waves propagating through the first silicon oxide film. The high-acoustic-velocity dielectric film is provided at a distance of about (t1+t2)×0.42 or less from a first main surface of the piezoelectric substrate in a thickness direction of the piezoelectric substrate.

Abstract: An elastic wave device includes a high-acoustic-velocity member, a low-acoustic-velocity film, a piezoelectric film, and am interdigital transducer electrode stacked in this order. The interdigital transducer electrode includes an intersecting region and outer edge regions. The intersecting region includes a central region located in the middle of the intersecting region in the direction in which electrode fingers extend and the inner edge regions located at the respective outer side portions of the central region. The electrode fingers in the inner edge regions have a larger thickness than in the central region. Each electrode finger has an incrased thickness portion. The increased thickness portion is made of a metal having a density d of about 5.5 g/cm3 or more and has a film thickenss equal to or smaller than a wavelength-normalized film thickness represented by T (%)=?0.1458d+4.8654.

Abstract: An elastic wave device includes a piezoelectric substrate, an IDT electrode including a first electrode layer located on the piezoelectric substrate and including one of Mo and W as a main component and a second electrode layer laminated on the first electrode layer and including Cu as a main component, and a dielectric film located on the piezoelectric substrate and covering the IDT electrode. The piezoelectric substrate is made of lithium niobate. The dielectric film is made of silicon oxide. The elastic wave device utilizes Rayleigh waves propagating along the piezoelectric substrate.

Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.

Abstract: An elastic wave device includes a piezoelectric layer, an IDT electrode on the piezoelectric layer, a high-acoustic-velocity member, a low-acoustic-velocity film between the high-acoustic-velocity member and the piezoelectric layer. The piezoelectric layer is made of lithium tantalate, the IDT electrode includes metal layers including an Al metal layer and a metal layer having a higher density than Al. Expression 1 is satisfied: 301.74667?10.83029×TLT?3.52155×TELE+0.10788×TLT2+0.01003×TELE2+0.03989×TLT×TELE?0 expression 1, where ? represents a wavelength defined by an electrode finger pitch of the IDT electrode, TLT (%) represents a normalized film thickness of the piezoelectric layer to the wavelength ?, and TELE (%) represents a normalized film thickness of the IDT electrode in terms of Al to the wavelength ?.