Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.

Abstract: A semiconductor module that comprises a plurality of semiconductor chips mounted on a single substrate and which readily diagnoses all the semiconductor chips. A plurality of semiconductor chips are mounted on a single substrate. The semiconductor module is provided with a mode signal pin for receiving a mode signal for requesting performance of a diagnostic operation, as well as with a result output pin for outputting diagnostic results. Further, each of the semiconductor chips is provided with a diagnostic circuit for diagnosing the status of the corresponding semiconductor chip. The semiconductor module is also provided with a diagnosis controller for controlling the diagnostic circuits such that all the semiconductor chips are diagnosed in parallel or serially after a mode signal for requesting a diagnostic operation has been supplied to the mode signal pin.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.