Abstract: In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back.

Abstract: A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

Abstract: A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell.

Abstract: In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated.

Abstract: In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

Abstract: A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

Abstract: A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask.

Abstract: A method and system for fabricating a flash memory array comprising a core area and a periphery area is disclosed. The method and system comprises depositing a layer of poly2 over the core area and the periphery area, selectively etching the core area, and selectively etching the poly2 only in the periphery area wherein the occurrence of stringers is reduced. Through the use of the preferred embodiment of the present invention, the core and periphery areas are etched separately after the deposition of the poly2, thereby reducing the occurrence of stringers at the core/periphery interface. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent transistors is substantially reduced.

Abstract: In the manufacture of sub 0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.

Abstract: A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.