Patents by Inventor Maria Clemens Y. Quinones
Maria Clemens Y. Quinones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9583454Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: GrantFiled: December 13, 2011Date of Patent: February 28, 2017Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Patent number: 8372690Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.Type: GrantFiled: January 13, 2011Date of Patent: February 12, 2013Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Ruben P. Madrid
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Publication number: 20120083071Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Patent number: 8106501Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: GrantFiled: December 12, 2008Date of Patent: January 31, 2012Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Publication number: 20110244633Abstract: Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Inventors: Ruben P. Madrid, Romel N. Manatad, Maria Clemens Y. Quinones
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Publication number: 20110133318Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.Type: ApplicationFiled: January 13, 2011Publication date: June 9, 2011Applicant: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Ruben P. Madrid
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Patent number: 7893548Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.Type: GrantFiled: March 24, 2008Date of Patent: February 22, 2011Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Ruben P. Madrid
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Patent number: 7824966Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: GrantFiled: August 19, 2009Date of Patent: November 2, 2010Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Jocel P. Gomez
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Publication number: 20100164078Abstract: Semiconductor packages and methods for making and using such semiconductor packages are described. The semiconductor packages contain a dual gauge heat sink exposed on an upper part of the package, a leadframe containing a gate lead and an exposed drain pad on a lower part of the package, and a semiconductor die containing an IC device located between the heat sink and the leadframe. The gate of the IC device is connected to the gate lead of the leadframe using a bond interconnect wire or a gate interconnect clip located and placed under the heat sink and in between the heat sink and main leadframe. Such a configuration provides both a simple design for the semiconductor package and a simple method of manufacturing. Other embodiments are described.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Ruben Madrid, Romel N. Manatad, Maria Clemens Y. Quinones
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Publication number: 20100148346Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Patent number: 7659531Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.Type: GrantFiled: April 13, 2007Date of Patent: February 9, 2010Assignee: Fairchild Semiconductor CorporationInventors: Yoon Hwa Choi, Yong Suk Kwon, Maria Clemens Y. Quinones
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Publication number: 20090311832Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: ApplicationFiled: August 19, 2009Publication date: December 17, 2009Inventors: Maria Clemens Y. QuiƱones, Jocel P. Gomez
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Patent number: 7626249Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die having a first surface comprising a die contact region, and a second surface. It also includes a leadframe structure having a die attach pad and a lead structure, where the semiconductor die is attached to the die attach pad. It also includes a flex clip connector comprising a flexible insulator, a first electrical contact region, and a second electrical contact region. The first electrical contact region of the flex clip connector is coupled to the die contact region and the second electrical contact region of the flex clip connector is coupled to the lead structure.Type: GrantFiled: January 10, 2008Date of Patent: December 1, 2009Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Jocel P. Gomez
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Publication number: 20090236702Abstract: Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: Maria Clemens Y. Quinones, Ruben P. Madrid
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Publication number: 20080251739Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.Type: ApplicationFiled: April 13, 2007Publication date: October 16, 2008Inventors: Yoon Hwa Choi, Yong Suk Kwon, Maria Clemens Y. Quinones
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Patent number: 7196313Abstract: An optocoupler package is disclosed. The optocoupler package includes a substrate comprising a leadframe and a molding compound, and a plurality of optocouplers, each optocoupler including (i) an optical emitter, (ii) an optical receiver, (iii) and an optically transmissive medium disposed between the optical emitter and optical receiver, where the optical emitter and the optical receiver are electrically coupled to the leadframe.Type: GrantFiled: April 2, 2004Date of Patent: March 27, 2007Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Rajeev Joshi
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Patent number: 7052938Abstract: A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such that the copper clip contacts drain regions of the bumped die and a lead rail. The chip device is manufactured by flip chipping a bumped die onto the leadframe and placing the copper clip on a backside of the trench die such that the backside of the trench die is coupled to the lead rail. The process involves reflowing the solder bumps on the bumped die and solder paste that is placed between the copper clip and the backside of the bumped die.Type: GrantFiled: February 4, 2005Date of Patent: May 30, 2006Assignee: Fairchild Semiconductor CorporationInventors: Maria Cristina B. Estacio, Maria Clemens Y. Quinones
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Patent number: 6870254Abstract: A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such that the copper clip contacts drain regions of the bumped die and a lead rail. The chip device is manufactured by flip chipping a bumped die onto the leadframe and placing the copper clip on a backside of; the trench die such that the backside of the trench die is coupled to the lead rail. The process involves reflowing the solder bumps on the bumped die and solder paste that is placed between the copper clip and the backside of the bumped die.Type: GrantFiled: April 13, 2000Date of Patent: March 22, 2005Assignee: Fairchild Semiconductor CorporationInventors: Maria Cristina B. Estacio, Maria Clemens Y. Quinones
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Patent number: 6777800Abstract: A semiconductor die package including a semiconductor die including a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.Type: GrantFiled: September 30, 2002Date of Patent: August 17, 2004Assignee: Fairchild Semiconductor CorporationInventors: Ruben Madrid, Maria Clemens Y. Quinones
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Patent number: 6762067Abstract: A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies therebetween and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.Type: GrantFiled: January 18, 2000Date of Patent: July 13, 2004Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Gilmore S. Baje, Maria Christina B. Estacio, Marvin R. Gestole, Oliver M. Ledon, Santos E. Mepieza