Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction.

Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction.

Abstract: A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

Abstract: A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.