Patents by Inventor Maria Galiano

Maria Galiano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6277347
    Abstract: A method and apparatus for abating a compound in a substrate processing system's effluent gases. The method of the present invention begins by introducing ozone and the effluent gases into an abatement device's combustion chamber. Energy is then applied to the effluent gas and ozone. The application of energy, such as thermal or radio frequency energy, then causes a reaction in and between the effluent gases and the ozone, thereby rendering the compound inert. The resultant gases produced are then exhausted out of the combustion chamber.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: August 21, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Ranald Stearns, Gary Sypherd, Stuardo Robles, Maria Galiano
  • Patent number: 6218268
    Abstract: A method for forming a BPSG film from a two-step deposition process and related apparatus and devices. A conformal layer of BPSG is deposited on a substrate. A more stable layer of BPSG is deposited at a higher deposition rate over the conformal layer. The method is suitable for filling trenches at least as narrow as 0.06 microns with aspect ratios of at least 5.5:1.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: April 17, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Ellie Yieh, Maria Galiano, Francimar Campana, Shankar Chandran
  • Patent number: 6177344
    Abstract: A multistep method for planarizing a silicon oxide insulating layer such as a deposited borophosphosilicate glass (BPSG) layer. The method includes several different planarization stages. During an initial, pre-planarization stage, a substrate having a BPSG layer deposited over it is loaded into a substrate processing chamber. Then, during a first planarization stage after the pre-planarization stage, oxygen and hydrogen are flowed into the substrate processing chamber to form a steam ambient in said chamber and the substrate is heated in the steam ambient from a first temperature to a second temperature. The first temperature is below a reflow temperature of the BPSG layer and the second temperature is sufficient to reflow the layer. After the substrate is heated to the second temperature during a second planarization stage, the temperature of the substrate and the conditions within the substrate processing chamber are maintained at conditions sufficient to reflow the BPSG layer in the steam ambient.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: January 23, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Richard A. Conti, Maria Galiano, Ellie Yieh
  • Patent number: 6009827
    Abstract: A method and apparatus for ramping down the deposition pressure in a SACVD process. The present invention also provides a method and apparatus for subsequently ramping up the pressure for a PECVD process in such a manner as to prevent unwanted reactions which could form a weak interlayer interface. In particular, the deposition pressure in the SACVD process is ramped down by stopping the flow of the silicon containing gas (preferably TEOS) and/or the carrier gas (preferably helium), while diluting the flow of ozone with oxygen. A ramp down of the pressure starts at the same time. The diluting of the ozone with oxygen limits reactions with undesired reactants at the end of a process.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: January 4, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Stuardo Robles, Visweswaren Sivaramakrishnan, Maria Galiano, Victoria Kithcart
  • Patent number: 5902494
    Abstract: A method and apparatus for preventing particles from dislodging from the interior of a process chamber by preventing DC bias spikes. Such DC bias spikes can be caused by variations in the power or pressure in a process chamber. DC bias spikes are prevented by ramping changes in the pressure at a rate which avoids the creation of such spikes. RF power is ramped down at a rate which avoids spikes.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: May 11, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Stefan Wolff, Maria Galiano
  • Patent number: 5814377
    Abstract: A method and apparatus for ramping down the deposition pressure in a SACVD process. The present invention also provides a method and apparatus for subsequently ramping up the pressure for a PECVD process in such a manner as to prevent unwanted reactions which could form a weak interlayer interface. In particular, the deposition pressure in the SACVD process is ramped down by stopping the flow of the silicon containing gas (preferably TEOS) and/or the carrier gas (preferably helium), while diluting the flow of ozone with oxygen. A ramp down of the pressure starts at the same time. The diluting of the ozone with oxygen, limits reactions with undesired reactants at the end of a process.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: September 29, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Stuardo Robles, Visweswaren Sivaramakrishnan, Maria Galiano, Victoria Kithcart
  • Patent number: 5356722
    Abstract: A process for depositing void-free silicon oxide layers over stepped topography comprising depositing a first silicon oxide seed layer which is doped with nitrogen from a plasma of tetraethoxysilane and a nitrogen-containing gas, and depositing thereover a silicon oxide layer from a mixture of tetraethoxysilane, ozone and oxygen at low temperatures to produce a silicon oxide layer having improved properties.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: October 18, 1994
    Assignee: Applied Materials, Inc.
    Inventors: Bang Nguyen, Ellie Yieh, Maria Galiano