Patents by Inventor Maria Luisa Gallese
Maria Luisa Gallese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446258Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: GrantFiled: October 2, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Patent number: 10170167Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: GrantFiled: May 23, 2016Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
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Patent number: 10037809Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: GrantFiled: October 2, 2017Date of Patent: July 31, 2018Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20180075913Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: ApplicationFiled: October 2, 2017Publication date: March 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20180047460Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Patent number: 9779839Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data.Type: GrantFiled: November 13, 2015Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Patent number: 9779826Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.Type: GrantFiled: July 24, 2017Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9754674Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: GrantFiled: October 7, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20170025181Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Patent number: 9513912Abstract: Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one type in the instruction set, executing a context switch instruction, and executing an instruction of a second type in the instruction set. in one such controller, a single machine executes instructions in an instruction set with instructions having an operational code, and instructions that do not have an operational code.Type: GrantFiled: July 27, 2012Date of Patent: December 6, 2016Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Maria-Luisa Gallese, Emanuele Sirizotti, Walter Di-Francesco
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Patent number: 9502125Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: GrantFiled: September 8, 2014Date of Patent: November 22, 2016Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20160267953Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
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Patent number: 9406388Abstract: In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.Type: GrantFiled: May 10, 2007Date of Patent: August 2, 2016Assignee: Micron Technology, Inc.Inventors: Luca De Santis, Maria Luisa Gallese, Giuliano Gennaro Imondi
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Patent number: 9349423Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: GrantFiled: September 3, 2014Date of Patent: May 24, 2016Assignee: Micron Technology, Inc.Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
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Publication number: 20160071619Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.Type: ApplicationFiled: November 13, 2015Publication date: March 10, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
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Publication number: 20160071605Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
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Publication number: 20160064052Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.Type: ApplicationFiled: September 3, 2014Publication date: March 3, 2016Inventors: Mauro Castelli, Luca De Santis, Luigi Pilolli, Maria Luisa Gallese
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Patent number: 9189440Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.Type: GrantFiled: July 14, 2014Date of Patent: November 17, 2015Assignee: Micron Technology, Inc.Inventors: Luigi Pilolli, Maria-Luisa Gallese, Mauro Castelli
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Publication number: 20150019787Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.Type: ApplicationFiled: July 14, 2014Publication date: January 15, 2015Inventors: Luigi Pilolli, Maria-Luisa Gallese, Mauro Castelli
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Patent number: 8804452Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.Type: GrantFiled: July 31, 2012Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventors: Luigi Pilolli, Maria-Luisa Gallese, Mauro Castelli