Patents by Inventor Maria Viviana Volpe

Maria Viviana Volpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8062976
    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: November 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Raffaele Vecchione, Luigi Giuseppe Occhipinti, Nunzia Malagnino, Rossana Scaldaferri, Maria Viviana Volpe
  • Patent number: 7976745
    Abstract: The present invention relates to a process for the preparation of a composite polymeric material containing nanometric inorganic inclusions comprising the steps of: mixing a polymer with a thermolytic precursor to provide a homogeneous dispersion of said at least one precursor and of said at least one polymer; subjecting said homogeneous dispersion to heating to provide a molten polymer and thermolytic fission of the precursor, generating the inclusions dispersed in the molten polymer.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: July 12, 2011
    Assignees: STMicroelectronics S.r.l., Universita degli Studi di Napoli Federico II
    Inventors: Raffaele Vecchione, Gianfranco Carotenuto, Valeria Casuscelli, Floriana Esposito, Salvatore Leonardi, Luigi Nicolais, Maria Viviana Volpe
  • Publication number: 20110027986
    Abstract: A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 3, 2011
    Applicant: STMicroelectronics S.r.l.
    Inventors: Raffaele VECCHIONE, Luigi Giuseppe OCCHIPINTI, Nunzia MALAGNINO, Rossana SCALDAFERRI, Maria Viviana VOLPE
  • Patent number: 7851294
    Abstract: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 14, 2010
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Andrea Basco, Maria Viviana Volpe, Maria Fortuna Bevilacqua, Valeria Casuscelli
  • Patent number: 7842826
    Abstract: A process performs solid phase synthesis of halogenated derivatives of fluorescein, and includes reacting fluorescein with a halide MX, wherein M is an alkali metal and X is a halogen, and Oxone® (2 KHSO5.KHSO4.K2SO4), at a temperature higher than or equal to 150° C. A structure uses a halogenated derivative of fluorescein selected from the group consisting of 2?,4?,5?-trichlorofluorescein, 2?,4?,5?,7?-tetrachlorofluorescein, 4?,5?-diiodofluorescein diacetate and 2?,4?,5?-triiodofluorescein as electro-bistable material in a non-volatile memory device.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: November 30, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maria Viviana Volpe, Angela Cimmino, Alessandro Pezzella, Aniello Palma
  • Publication number: 20100296340
    Abstract: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel.
    Type: Application
    Filed: September 8, 2006
    Publication date: November 25, 2010
    Inventors: Andrea Basco, Maria Viviana Volpe, Maria Fortuna Bevilacqua, Valeria Casuscelli
  • Publication number: 20090299082
    Abstract: The invention relates to epoxy functionalized carbon nanotubes (CNTs) and methods of forming the same, and more particularly to inclusion of the epoxy functionalized CNTs as fillers in electronic applications, e.g., semiconductor devices and device packaging. More particularly, CNT-based epoxy resin composites are employed as materials for electronic packaging applications and the inclusion of CNTs as fillers chemically linked to epoxy resin macromolecules. The resulting materials showed improved chemical-physical features in terms of mechanical, thermal and electrical properties.
    Type: Application
    Filed: March 25, 2009
    Publication date: December 3, 2009
    Applicants: STMicroelectronics Asia Pacific Pte Ltd., STMicroelectronics Srl, Nanyang Technological University
    Inventors: Charles Baudot, Maria Viviana Volpe, Jeng Chien Kong, Cher Ming Tan