Patents by Inventor Marian Kuruc

Marian Kuruc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Insulated gate bipolar device and manufacturing method thereof
    Patent number: 10134886
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20170323958
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian KURUC, Juraj VAVRO
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20170271489
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Application
    Filed: June 7, 2016
    Publication date: September 21, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian KURUC, Juraj VAVRO
  • Semiconductor device and method of manufacture
    Patent number: 9768285
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Semiconductor device having a patterned gate dielectric
    Patent number: 9385202
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 5, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • SEMICONDUCTOR DEVICE HAVING A PATTERNED GATE DIELECTRIC
    Publication number: 20150102403
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Method of forming a semiconductor device having a patterned gate dielectric and structure therefor
    Patent number: 8946002
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A PATTERNED GATE DIELECTRIC AND STRUCTURE THEREFOR
    Publication number: 20140027813
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: Marian Kuruc, Iuraj Vavro