Abstract: An integrated device includes a die attach pad, a main die, a stacked die, and a mold compound. The main die has a first (e.g., bottom) surface attached to the die attach pad and has a second (e.g., top) surface. The stacked die is attached to the second surface of the main die using, for example, an adhesive film. The main die and the stacked die include silicon crystal. The mold compound encapsulates the die attach pad, the main die, and the stacked die.

Abstract: A laterally-diffused metal-oxide-semiconductor (LDMOS) transistor includes a first well of a first conductivity type, a source of a second conductivity type formed in the first well, a drift region of the second conductivity type formed in the first well, and a second well of the second conductivity type formed in the first well and below the drift region. The drift region is separated from the source. The LDMOS transistor further includes a drain of the second conductivity type formed in the drift region, and includes a concentrator of the second conductivity type formed in the drift region and separated from the drain. A distance between the concentrator and the source is less than a distance between the drain and the source.

Abstract: A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Abstract: A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Abstract: A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.

Abstract: A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.