Patents by Inventor Marianne Berolini

Marianne Berolini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111993
    Abstract: The present invention is directed to a surface mount coupling capacitor. The coupling capacitor includes a main body containing at least two sets of alternating dielectric layers and internal electrode layers wherein each set of alternating dielectric layers and internal electrode layers contains a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. The coupling capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposing the top surface of the coupling capacitor. The capacitor includes one or more dielectric regions including one or more air voids.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 3, 2025
    Inventors: Marianne Berolini, Craig Nies, Jeffrey Horn, Joseph M. Hock
  • Publication number: 20250106979
    Abstract: A heat sink component can include a body including a thermally conductive material that is electrically non-conductive, a lower conductive layer formed over a bottom surface of the body and electrically connected with the ground plane layer, and an upper conductive layer formed over a top surface of the body. The heat sink component can have a length in an X-direction that is parallel with the top surface of the body and a thickness in a direction perpendicular to the top surface. A ratio of the length to the thickness can be greater than about 7.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Cory Nelson, Jeff Borgman, Marianne Berolini
  • Publication number: 20250079321
    Abstract: Vertically oriented interposer stacks, assemblies, and methods are provided. For example, a vertically oriented interposer stack includes a plurality of interposers and a plurality of components. Each component is disposed between adjacent interposers. Each interposer includes a first side surface opposite a second side surface along the vertical direction. The first side surface and the second side surface each extend along the longitudinal direction from a first end surface to a second end surface. Each interposer has a first external termination formed on the first side surface and a second external termination formed on the first side surface. The first and second external terminations are spaced apart along the longitudinal direction. The interposers are stacked along the lateral direction such that the first external terminations are generally aligned with one another along the lateral direction and the second external terminations are generally aligned with one another along the lateral direction.
    Type: Application
    Filed: August 15, 2024
    Publication date: March 6, 2025
    Inventors: Jonathan Herr, Cory Nelson, Marianne Berolini, Joseph Hock
  • Publication number: 20250079419
    Abstract: Vertically oriented component stacks, assemblies, and methods are provided. For example, a vertically oriented component stack includes a plurality of components that each include a first side surface opposite a second side surface along a vertical direction. The first and second side surfaces each extend along a longitudinal direction from a first end surface to a second end surface. Each component has a first external termination and a second external termination formed on the first side surface. The first external termination is spaced apart from the second external termination along the longitudinal direction. The plurality of components are stacked along the lateral direction such that the first external terminations of the plurality of components are generally aligned with one another along the lateral direction and the second external terminations of the plurality of components are generally aligned with one another along the lateral direction.
    Type: Application
    Filed: August 15, 2024
    Publication date: March 6, 2025
    Inventors: Jonathan Herr, Cory Nelson, Marianne Berolini, Joseph Hock
  • Publication number: 20250079404
    Abstract: A vertical component stack, assembly, and method are provided. For example, a vertical component stack may include a plurality of components that each include an upper surface and a lower surface opposite the upper surface along a vertical direction. The plurality of components are stacked along the vertical direction such that a lower surface of a second component of the plurality of components is disposed over an upper surface of a first component of the plurality of components. An input and an output of each component of the plurality of components is exposed on a lower surface of the first component of the plurality of components.
    Type: Application
    Filed: August 15, 2024
    Publication date: March 6, 2025
    Inventors: Jonathan Herr, Cory Nelson, Marianne Berolini, Joseph Hock
  • Patent number: 12205766
    Abstract: A broadband multilayer ceramic capacitor can include at least one active electrode layer including a first active electrode and a second active electrode. The first active electrode can have a central portion extending away from a base portion in a longitudinal direction. The second active electrode can include at least one arm extending away from a base portion towards the first end and overlapping the central portion of the first active electrode. A first shield electrode in a shield electrode region can have a central portion extending from a base portion. A second shield electrode can include an arm overlapping the central portion of the first shield electrode in the longitudinal direction. The shield electrode region can be spaced apart from the active electrode region by a shield-to-active distance that is greater than an active electrode spacing distance between respective active electrodes of the plurality of active electrodes.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: January 21, 2025
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Marianne Berolini, Jeffrey A Horn
  • Publication number: 20250022638
    Abstract: A varistor can include a monolithic body including a plurality of dielectric layers stacked in a Z-direction that is perpendicular to a longitudinal direction. The monolithic body can have a first end and a second end that is spaced apart from the first end in the longitudinal direction. A first external terminal can be disposed along the first end. A second external terminal can be disposed along the second end. A first plurality of electrodes can be connected with the first external terminal and can extend from the first end towards the second end of the monolithic body. A second plurality of electrodes can be connected with the second external terminal and can extend from the second end towards the first end of the monolithic body. At least one of the first external terminal or the second external terminal can include a conductive polymeric composition.
    Type: Application
    Filed: September 25, 2024
    Publication date: January 16, 2025
    Inventors: Palaniappan Ravindranathan, Marianne Berolini, Michael W. Kirk
  • Patent number: 12200853
    Abstract: A heat sink component can include a body including a thermally conductive material that is electrically non-conductive, a lower conductive layer formed over a bottom surface of the body and electrically connected with the ground plane layer, and an upper conductive layer formed over a top surface of the body. The heat sink component can have a length in an X-direction that is parallel with the top surface of the body and a thickness in a direction perpendicular to the top surface. A ratio of the length to the thickness can be greater than about 7.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: January 14, 2025
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Cory Nelson, Jeff Borgman, Marianne Berolini
  • Patent number: 12148575
    Abstract: An integrated component may include a multilayer capacitor include a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The integrated component may include a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 19, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Michael W. Kirk, Marianne Berolini
  • Publication number: 20240379649
    Abstract: Single layer capacitors and circuit boards having such capacitors are provided. A circuit board can include a circuit board substrate having a mounting surface and a single layer capacitor at least partially embedded therein. The single layer capacitor includes a first conductive layer formed over at least a portion of a substrate first surface and a second conductive layer formed over at least a portion of a substrate second surface. At least one of the first or second conductive layers has a thickness that is at least about 5 microns. A method of forming a single layer capacitor includes depositing a first conductive layer over at least a portion of a substrate first surface and depositing a second conductive layer over at least a portion of a substrate second surface. At least one of the first or second conductive layers has a thickness that is at least about 5 microns.
    Type: Application
    Filed: April 11, 2024
    Publication date: November 14, 2024
    Inventors: Cory Nelson, Marianne Berolini, Jessica Parry, Jonathan Shealy
  • Patent number: 12131848
    Abstract: A varistor can include a monolithic body including a plurality of dielectric layers stacked in a Z-direction that is perpendicular to a longitudinal direction. The monolithic body can have a first end and a second end that is spaced apart from the first end in the longitudinal direction. A first external terminal can be disposed along the first end. A second external terminal can be disposed along the second end. A first plurality of electrodes can be connected with the first external terminal and can extend from the first end towards the second end of the monolithic body. A second plurality of electrodes can be connected with the second external terminal and can extend from the second end towards the first end of the monolithic body. At least one of the first external terminal or the second external terminal can include a conductive polymeric composition.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 29, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Palaniappan Ravindranathan, Marianne Berolini, Michael W. Kirk
  • Publication number: 20240292540
    Abstract: The present disclosure provides multicomponent connector assemblies and methods of forming such assemblies. For example, a multicomponent connector assembly includes a multicomponent connector having first and support members and also includes a plurality of components disposed between the first and second support members. At least one of the plurality of components may be a heat sink component configured to conduct heat from a first area to a second area. Additionally, or alternatively, the plurality of components may include a capacitor, a resistor, a varistor, an inductor, or the like. In at least some connectors, a plurality of slots are defined, and at least one component is disposed between the first and support members in a respective one slot of the plurality of slots.
    Type: Application
    Filed: February 21, 2024
    Publication date: August 29, 2024
    Inventors: Ronald Demcko, Cory Nelson, Marianne Berolini
  • Patent number: 12058845
    Abstract: A filter assembly is disclosed that includes a monolithic filter having a surface and a heat sink coupled to the surface of the monolithic filter. The heat sink includes a layer of thermally conductive material that can have a thickness greater than about 0.02 mm. The heat sink may provide electrical shielding for the monolithic filter. In some embodiments, the filter assembly may include an organic dielectric material, such as liquid crystalline polymer or polyphenyl ether. In some embodiments, the filter assembly may include an additional monolithic filter.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 6, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Kwang Choi, Marianne Berolini, Michael W. Kirk, Hector Fuentes, Jonathan C. Herr, Bryan R. Seither
  • Patent number: 12051548
    Abstract: A low inductance component may include a multilayer, monolithic device including a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The lead(s) may be coupled with the first active termination, second active termination, and/or the at least one ground termination. The lead(s) may have respective length(s) and maximum width(s). A ratio of the length(s) to the respective maximum width(s) of the lead(s) may be less than about 20.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: July 30, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Michael W. Kirk, Marianne Berolini
  • Publication number: 20240249880
    Abstract: Multilayer capacitors are provided. For example, a multilayer capacitor may include first and second terminals adjacent first and second opposing end surfaces, respectively, and a plurality of active electrode layers, each active electrode layer including a first active electrode electrically connected with the first terminal and a second active electrode electrically connected with the second terminal. The first active electrode may be spaced apart from the second active electrode in a lengthwise direction to form an active electrode end gap. The multilayer capacitor also may include a plurality of floating electrode layers, including topmost and bottommost floating electrode layers. The plurality of active electrode layers may be an odd number such that a topmost active electrode layer is disposed between the topmost floating electrode layer and a top surface and a bottommost active electrode layer is disposed between the bottommost floating electrode layer and a bottom surface.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 25, 2024
    Inventors: Cory Nelson, Jeffrey Horn, Marianne Berolini
  • Publication number: 20240234038
    Abstract: A single layer capacitor can include a substrate having a first surface and a second surface opposite the first surface. A resistive layer can be formed over at least a portion of the first surface of the substrate. A first conductive layer can be formed over at least a portion of the resistive layer. A second conductive layer can be formed over at least a portion of the second surface of the substrate. As such, the single layer capacitor can include a resistor and a capacitor formed in series with one another.
    Type: Application
    Filed: October 18, 2023
    Publication date: July 11, 2024
    Inventors: Ronald S. Demcko, Cory Nelson, Marianne Berolini, Jeff Borgman
  • Publication number: 20240234591
    Abstract: A metal-oxide-semiconductor (MOS) capacitor can include a substrate comprising a semiconductor material, an oxide layer formed over a first surface of the substrate, a resistive layer formed over at least a portion of the oxide layer, and a conductive layer formed over at least a portion of the resistive layer. As such, the MOS capacitor can include a resistor and a capacitor formed in series with one another.
    Type: Application
    Filed: October 18, 2023
    Publication date: July 11, 2024
    Inventors: Ronald S. Demcko, Cory Nelson, Marianne Berolini, Jeff Borgman
  • Patent number: 12033775
    Abstract: A varistor array can include a monolithic body including a plurality of dielectric layers. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal on a first end of the monolithic body, a first plurality of electrodes connected with the first external terminal, a second external terminal on a second end of the monolithic body, and a second plurality of electrodes connected with the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes at an overlapping area that is insensitive to a relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is less than a threshold. A second varistor can be formed in the monolithic body that is distinct from the first varistor.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: July 9, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Michael W. Kirk, Marianne Berolini, Palaniappan Ravindranathan
  • Patent number: 12033801
    Abstract: A broadband multilayer ceramic capacitor may include a first external terminal and a second external terminal. A bottom portion of the first external terminal may be spaced apart from a bottom portion of the second external terminal by a bottom external terminal spacing distance. A first active electrode layer may include a first active electrode connected with the first external terminal and a second active electrode connected with the second external terminal and co-planar with the first electrode. A second active electrode layer may include a third active electrode connected to the first external terminal and a fourth active electrode connected to the second external terminal and co-planar with the fourth electrode. The first active electrode may overlap the fourth active electrode in the longitudinal direction. A ratio of a length of the capacitor to the bottom external terminal spacing distance may be greater than about 4.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: July 9, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Marianne Berolini, Jeffrey A Horn
  • Patent number: 11984262
    Abstract: A multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers and a plurality of electrode regions. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shield electrode region. The active electrode region may be located between the dielectric region and the shield electrode region in a Z-direction. The dielectric region may extend from the active electrode region to the top surface of the broadband multilayer ceramic capacitor. The capacitor may include a plurality of active electrodes arranged within the active electrode region and at least one shield electrode arranged within the shield electrode region. The dielectric region may be free of electrode layers that extend greater than 25% of a length of the capacitor. A ratio of a capacitor thickness to a thickness of the dielectric region may be less than about 20.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 14, 2024
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Marianne Berolini, Jeffrey A. Horn, Richard C. VanAlstine