Patents by Inventor Marianne Germain
Marianne Germain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847412Abstract: A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: —a III-N layer; —a AI-III-N layer on top of the III-N layer; —a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.Type: GrantFiled: October 12, 2012Date of Patent: December 19, 2017Assignee: EpiGaN nvInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 9748331Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: GrantFiled: December 10, 2015Date of Patent: August 29, 2017Assignee: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 9543424Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).Type: GrantFiled: July 6, 2012Date of Patent: January 10, 2017Assignee: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20160099309Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: ApplicationFiled: December 10, 2015Publication date: April 7, 2016Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 9230803Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: GrantFiled: July 6, 2012Date of Patent: January 5, 2016Assignee: Epigan NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20150008444Abstract: A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: a III-N layer; a AI-III-N layer on top of the III-N layer; a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.Type: ApplicationFiled: October 12, 2012Publication date: January 8, 2015Applicant: EPIGAN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 8809138Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.Type: GrantFiled: October 12, 2012Date of Patent: August 19, 2014Assignee: IMECInventors: Joff Derluyn, Farid Medjdoub, Marianne Germain
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Publication number: 20140167114Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: ApplicationFiled: July 6, 2012Publication date: June 19, 2014Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20140159119Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).Type: ApplicationFiled: July 6, 2012Publication date: June 12, 2014Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20130237021Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.Type: ApplicationFiled: February 27, 2013Publication date: September 12, 2013Applicants: Katholieke Universiteit Leuven, IMECInventors: Joff Derluyn, Steven Boeykens, Marianne Germain, Gustaaf Borghs
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Patent number: 8399911Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.Type: GrantFiled: June 6, 2007Date of Patent: March 19, 2013Assignee: IMECInventors: Joff Derluyn, Steven Boeykens, Marianne Germain, Gustaaf Borghs
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Patent number: 8309987Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.Type: GrantFiled: July 14, 2009Date of Patent: November 13, 2012Assignee: IMECInventors: Joff Derluyn, Farid Medjdoub, Marianne Germain
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Patent number: 7772055Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.Type: GrantFiled: February 4, 2009Date of Patent: August 10, 2010Assignee: IMECInventors: Marianne Germain, Joff Derluyn, Maarten Leys
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Publication number: 20100012977Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al?. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.Type: ApplicationFiled: July 14, 2009Publication date: January 21, 2010Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Joff Derluyn, Farid Medjdoub, Marianne Germain
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Publication number: 20090191674Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.Type: ApplicationFiled: February 4, 2009Publication date: July 30, 2009Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Marianne Germain, Joff Derluyn, Maarten Leys
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Patent number: 7547928Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.Type: GrantFiled: June 29, 2005Date of Patent: June 16, 2009Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Marianne Germain, Joff Derluyn, Maarten Leys
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Patent number: 7327036Abstract: The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on the second layer. The present invention further is related to methods of production and to intermediate or template devices highly suitable for the epitaxial growth of a high quality Group III-nitride layer.Type: GrantFiled: December 21, 2004Date of Patent: February 5, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Gustaaf Borghs, Stefan Degroote, Marianne Germain
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Publication number: 20080006845Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.Type: ApplicationFiled: June 6, 2007Publication date: January 10, 2008Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Katholieke Universiteit LeuvenInventors: Joff Derluyn, Steven Boeykens, Marianne Germain, Gustaaf Borghs
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Publication number: 20060006414Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.Type: ApplicationFiled: June 29, 2005Publication date: January 12, 2006Inventors: Marianne Germain, Joff Derluyn, Maarten Leys
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Publication number: 20050199883Abstract: The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on the second layer. The present invention further is related to methods of production and to intermediate or template devices highly suitable for the epitaxial growth of a high quality Group III-nitride layer.Type: ApplicationFiled: December 21, 2004Publication date: September 15, 2005Inventors: Gustaaf Borghs, Stefan Degroote, Marianne Germain