Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: Semiconductor devices including a diode and a resistor are disclosed herein. An example of a semiconductor device includes a substrate having a surface. A first doped semiconductive region is disposed in the substrate below the surface. A second doped semiconductive region is disposed in the substrate and extends between the surface and the first doped semiconductive region. The second doped semiconductive region is at least partially in contact with the first doped semiconductive region. The first doped semiconductive region and the second doped semiconductive region together define an isolation tank. A third doped semiconductive region is disposed in the isolation tank and is in contact with the surface. The second doped semiconductive region and the third doped semiconductive region form a diode. At least one opening in the isolation tank forms a resistive path for current to flow between the substrate and the third doped semiconductive region.

Abstract: Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.

Abstract: Semiconductor devices including a diode and a resistor are disclosed herein. An example of a semiconductor device includes a substrate having a surface. A first doped semiconductive region is disposed in the substrate below the surface. A second doped semiconductive region is disposed in the substrate and extends between the surface and the first doped semiconductive region. The second doped semiconductive region is at least partially in contact with the first doped semiconductive region. The first doped semiconductive region and the second doped semiconductive region together define an isolation tank. A third doped semiconductive region is disposed in the isolation tank and is in contact with the surface. The second doped semiconductive region and the third doped semiconductive region form a diode. At least one opening in the isolation tank forms a resistive path for current to flow between the substrate and the third doped semiconductive region.

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: An integrated circuit includes an electrostatic discharge (ESD) detection circuit which detects an ESD event and generates an event signal. In response to that event signal, a control circuit controls the operation of a buffer circuit to function in an additional mode wherein the normal differential operation of the buffer circuit is disabled and the buffer circuit is instead configured to form a conduction path between supply rails to discharge the ESD event. Preferably, a plurality of buffer circuits are driven in parallel by the control circuit to function in the additional mode to form parallel discharge paths for the ESD event. Multiple ESD detection circuits may be provided, and any one of those detection circuits can trigger the control circuitry to place all of the buffer circuits in the additional mode.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating.

Abstract: An integrated circuit includes an electrostatic discharge (ESD) detection circuit which detects an ESD event and generates an event signal. In response to that event signal, a control circuit controls the operation of a buffer circuit to function in an additional mode wherein the normal differential operation of the buffer circuit is disabled and the buffer circuit is instead configured to form a conduction path between supply rails to discharge the ESD event. Preferably, a plurality of buffer circuits are driven in parallel by the control circuit to function in the additional mode to form parallel discharge paths for the ESD event. Multiple ESD detection circuits may be provided, and any one of those detection circuits can trigger the control circuitry to place all of the buffer circuits in the additional mode.

Abstract: An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode.