Patents by Inventor MARIANO LAYSON CHING, JR.
MARIANO LAYSON CHING, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923275Abstract: A lead-frame assembly is disclosed, for a semiconductor die and comprising a die attach pad and a plurality of elongate leads spaced apart therefrom; wherein each elongate lead has a first proximal end portion, a second distal end portion and a middle portion therebetween; wherein the die attach pad and each of the plurality of elongate leads each comprise a coating-free portion, and a coated portion having a coating material thereon; wherein a part of a perimeter of the die attach pad proximal each lead is comprised in the coating-free portion, and wherein the proximal end portion of each elongate lead is comprised in the coating-free portion. Associated package assemblies and methods are also disclosed.Type: GrantFiled: August 27, 2021Date of Patent: March 5, 2024Assignee: NXP USA, Inc.Inventors: Allen Marfil Descartin, Mariano Layson Ching, Jr., Jun Li
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Publication number: 20230124619Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.Type: ApplicationFiled: November 2, 2021Publication date: April 20, 2023Inventors: You Ge, Zhijie Wang, Yit Meng Lee, Mariano Layson Ching, JR.
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Publication number: 20220415761Abstract: A lead-frame assembly is disclosed, for a semiconductor die and comprising a die attach pad and a plurality of elongate leads spaced apart therefrom; wherein each elongate lead has a first proximal end portion, a second distal end portion and a middle portion therebetween; wherein the die attach pad and each of the plurality of elongate leads each comprise a coating-free portion, and a coated portion having a coating material thereon; wherein a part of a perimeter of the die attach pad proximal each lead is comprised in the coating-free portion, and wherein the proximal end portion of each elongate lead is comprised in the coating-free portion. Associated package assemblies and methods are also disclosed.Type: ApplicationFiled: August 27, 2021Publication date: December 29, 2022Inventors: Allen Marfil Descartin, Mariano Layson Ching, JR., Jun Li
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Patent number: 10847449Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.Type: GrantFiled: March 28, 2019Date of Patent: November 24, 2020Assignee: NXP USA, INC.Inventors: Meijiang Song, Allen Marfil Descartin, Mariano Layson Ching, Jr., Lidong Zhang, Jun Li
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Patent number: 10734327Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.Type: GrantFiled: January 3, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Mariano Layson Ching, Jr., Burton Jesse Carpenter, Jinmei Liu, Yit Meng Lee, Allen Marfil Descartin
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Patent number: 10734311Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.Type: GrantFiled: January 7, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Mariano Layson Ching, Jr., Burton Jesse Carpenter, Lidong Zhang, Kendall Dewayne Phillips, Quan Chen, Meng Kong Lye
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Publication number: 20200203258Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.Type: ApplicationFiled: March 28, 2019Publication date: June 25, 2020Inventors: Meijiang Song, Allen Marfil Descartin, Mariano Layson Ching, JR., Lidong Zhang, Jun Li
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Publication number: 20200203289Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.Type: ApplicationFiled: January 3, 2019Publication date: June 25, 2020Inventors: Mariano Layson CHING, JR., Burton Jesse Carpenter, Jinmei Liu, Yit Meng Lee, Allen Marfil Descartin
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Publication number: 20200203262Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.Type: ApplicationFiled: January 7, 2019Publication date: June 25, 2020Inventors: Mariano Layson CHING, JR., Burton Jesse CARPENTER, Lidong ZHANG, Kendall Dewayne PHILLIPS, Quan CHEN, Meng Kong LYE
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Patent number: 10446476Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.Type: GrantFiled: March 19, 2018Date of Patent: October 15, 2019Assignee: NXP USA, Inc.Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
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Publication number: 20190088576Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.Type: ApplicationFiled: March 19, 2018Publication date: March 21, 2019Inventors: LEO M. HIGGINS, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, JR., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
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Patent number: 10151658Abstract: An integrated circuit (IC) device includes a pressure sensor die, a flexible gel covering a least a pressure-sensing region of the die, and a flexible diaphragm covering the gel. The IC device has encapsulant and a lid that define a cavity above the diaphragm. The lid has an aperture that enables proximate ambient air pressure outside the device to be sensed by the pressure-sensing region through the flexible diaphragm and the flexible gel. The diaphragm protects the gel material from potentially harmful ambient materials. The diaphragm may be a part of the lid.Type: GrantFiled: November 20, 2016Date of Patent: December 11, 2018Assignee: NXP USA, INC.Inventors: Mariano Layson Ching, Jr., Allen M. Descartin, Alexander M. Arayata
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Publication number: 20170292884Abstract: An integrated circuit (IC) device includes a pressure sensor die, a flexible gel covering a least a pressure-sensing region of the die, and a flexible diaphragm covering the gel. The IC device has encapsulant and a lid that define a cavity above the diaphragm. The lid has an aperture that enables proximate ambient air pressure outside the device to be sensed by the pressure-sensing region through the flexible diaphragm and the flexible gel. The diaphragm protects the gel material from potentially harmful ambient materials. The diaphragm may be a part of the lid.Type: ApplicationFiled: November 20, 2016Publication date: October 12, 2017Inventors: MARIANO LAYSON CHING, JR., ALLEN M. DESCARTIN, ALEXANDER M. ARAYATA
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Patent number: 9190353Abstract: A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of the base side is exposed through the central window. A semiconductor chip is secured to the superior side of the substrate. The semiconductor chip is electrically connected to the plurality of leads and the substrate. A mold compound covers at least portions of the lead frame, the substrate and the semiconductor chip. The chip package can be electrically connected to other devices or a circuit board by way of the leads and BGA pads of the substrate exposed in the central window.Type: GrantFiled: December 30, 2013Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Mariano Layson Ching, Jr., Allen M. Descartin, Bo Li
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Publication number: 20140252581Abstract: A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of the base side is exposed through the central window. A semiconductor chip is secured to the superior side of the substrate. The semiconductor chip is electrically connected to the plurality of leads and the substrate. A mold compound covers at least portions of the lead frame, the substrate and the semiconductor chip. The chip package can be electrically connected to other devices or a circuit board by way of the leads and BGA pads of the substrate exposed in the central window.Type: ApplicationFiled: December 30, 2013Publication date: September 11, 2014Inventors: MARIANO LAYSON CHING, JR., Allen M. Descartin, Bo Li