Patents by Inventor Mariappan HARIHARAPUTHIRAN
Mariappan HARIHARAPUTHIRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735154Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.Type: GrantFiled: October 20, 2015Date of Patent: August 15, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
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Publication number: 20170162688Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.Type: ApplicationFiled: February 15, 2017Publication date: June 8, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Dae G. Yang, Mariappan Hariharaputhiran, Jing Wan
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Patent number: 9608086Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.Type: GrantFiled: May 20, 2014Date of Patent: March 28, 2017Assignee: GLOBAL FOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Dae G. Yang, Mariappan Hariharaputhiran, Jing Wan
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Publication number: 20160043081Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
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Publication number: 20150340461Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Andy Chih-Hung Wei, Dae G. Yang, Mariappan Hariharaputhiran, Jing Wan
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Patent number: 9196499Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.Type: GrantFiled: March 26, 2014Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
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Publication number: 20150333067Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
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Publication number: 20150287595Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Andy WEI, Mariappan HARIHARAPUTHIRAN, Dae Geun YANG, Dae-Han CHOI, Xiang HU, Richard J. CARTER, Akshey SEHGAL
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Publication number: 20150279684Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Dae-han Choi, Dae Geun Yang, Xiang Hu, Mariappan Hariharaputhiran
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Patent number: 9147696Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: GrantFiled: October 1, 2013Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
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Publication number: 20150270175Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Xiang Hu, Andy Chih-Hung Wei, Dae-han Choi, Mariappan Hariharaputhiran, Weihua Tong, Dae Geun Yang, Akshey Sehgal, Jing Wan
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Patent number: 9105478Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: GrantFiled: October 28, 2013Date of Patent: August 11, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy Wei, Mariappan Hariharaputhiran, Dae Geun Yang, Dae-Han Choi, Xiang Hu, Richard J. Carter, Akshey Sehgal
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Publication number: 20150214345Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing Wan, Jinping Liu, Churamani Gaire, Mariappan Hariharaputhiran, Andy Chih-Hung Wei, Bharat V. Krishnan, Cuiqin Xu, Michael Ganz
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Publication number: 20150115418Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Andy WEI, Mariappan HARIHARAPUTHIRAN, Dae Geun YANG, Dae-Han CHOI, Xiang HU, Richard J. CARTER, Akshey SEHGAL
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Publication number: 20150091094Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE