Abstract: The method of buffering packets in a digital communications device includes defining an n-level hierarchy of memory partitions, wherein each non-top level partition has one or more child partitions at an immediately lower level of the hierarchy. The memory partitions at the top-most level are pre-configured with a target memory occupancy size, and the target occupancy for each memory partition situated at a lower level is recursively computed in a dynamic manner based on the aggregate congestion of its parent partition, until the target occupancies for the bottom-most memory partitions are determined. Each traffic flow which uses the buffer is associated with one of the memory partitions at the bottom-most level of the hierarchy and packet discard is enabled in the event the actual memory occupancy of a traffic flow exceeds its target occupancy.

Abstract: The method of buffering packets in a digital communications device includes defining an n-level hierarchy of memory partitions, wherein each non-top level partition has one or more child partitions at an immediately lower level of the hierarchy. The memory partitions at the top-most level are pre-configured with a target memory occupancy size, and the target occupancy for each memory partition situated at a lower level is recursively computed in a dynamic manner based on the aggregate congestion of its parent partition, until the target occupancies for the bottom-most memory partitions are determined. Each traffic flow which uses the buffer is associated with one of the memory partitions at the bottom-most level of the hierarchy and packet discard is enabled in the event the actual memory occupancy of a traffic flow exceeds its target occupancy.

Abstract: A shaping algorithm for use in a queuing system in which there is no background process for detecting clock wrap around. The algorithm applies to Asynchronous Transfer Mode (ATM) applications and to the different categories of service connections specified by the ATM Forum. The algorithm is implemented by a time slotted calendar system to shape cell streams into conformance with network traffic descriptors. The calendar register is constrained to positive values to ensure valid results from the maximum functions carried out by the Algorithm. The register is divided into quadrants and the location of theoretical cell emission times relative to current and next time slots within the quadrants is used to detect clock wrap around.