Abstract: A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from logic for performing snoop actions. This logic split permits increased throughput because pending snoop queries must no longer wait until snoop actions complete. Two state machines are disclosed: a pipeline state machine for snoop queries; and a snoop action state machine, for executing the split logic handling snoop requests.

Abstract: A computer system including a first multiprocessor system connected to a system bus and adapted to forward first and second load requests to the system bus where the first load request precedes the second load request. The system further includes a second multiprocessor system connected to the system bus. The second multiprocessor system includes a memory subsystem comprised of first and second cache levels arranged such that an operation that retrieves data from the first cache level is arbitrated through the second cache level before the data becomes available to the system bus. A snoop control state machine of the second multiprocessor system is adapted to stall arbitration of a second operation initiated in the second cache level responsive to the second load request until a first operation initiated in the first cache level responsive to the first load request has been arbitrated through the second cache level.

Abstract: A memory subsystem for use with a multiprocessor computer system. The memory subsystem includes an operation block adapted for queuing an operation that misses in an L1 cache of a multiprocessor. The multiprocessor is comprised of a set of processors, preferably fabricated on a single semiconductor substrate and packaged in a single device package. The memory subsystem further includes an arbiter that is configured to receive external snoop operations from a bus interface unit and a queued operation from the operation block. The arbiter is configured to select and initiate one of received operations. Coherency is maintained by forwarding the address associated with the operation selected by the arbiter to each of a plurality of coherency units. In this manner, external and internal snoop addresses are arbitrated at a single point to produce a single subsystem snoop address that is propagated to each coherency unit.

Abstract: Each processor (101, 102, 103) in a multiple processor system (100) includes a contingent response unit (121, 122, 123). Each contingent response unit (121, 122, 123) includes a pending operation unit (200) for identifying each pending address bus operation from the respective processor which specifies an address matching a snoop address from another processor. A snoop pipeline is associated with the pending operation unit (200) and includes a plurality of pipeline stages (206). Each snoop pipeline stage (206) has a contingent response flag location (207) and an identifier location (208). When a pending operation from the processor specifies an address which is matched by a younger operation from another processor, a contingent response flag control arrangement uses information from the pending operation unit (200) to set a contingent response flag in a first snoop pipeline stage (206).