Patents by Inventor MARIE KRYSAK

MARIE KRYSAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953826
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Patent number: 11955343
    Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Marie Krysak, James M. Blackwell, Florian Gstrein, Kent N. Frasure
  • Patent number: 11955377
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Robert L Bristol, James M. Blackwell, Rami Hourani, Marie Krysak
  • Publication number: 20240071917
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 11874600
    Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Marie Krysak, James M. Blackwell, Robert L. Bristol, Florian Gstrein
  • Patent number: 11862463
    Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Marie Krysak, Florian Gstrein, Manish Chandhok
  • Patent number: 11854787
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 11846883
    Abstract: A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Robert Bristol, Marie Krysak, Lauren Doyle, James Blackwell, Eungnak Han
  • Publication number: 20220262722
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 11406972
    Abstract: Catalysts for facilitating cross-linking of liquid precursors into solid dielectric materials are disclosed. Initially, catalysts are protected, either by coordination with other compounds or by conversion to an ionic salt. Protection prevents catalysts from facilitating cross-linking unless activated. A catalyst is activated upon receiving an excitation, e.g. thermal excitation by heating. Upon receiving an excitation, protection of a catalyst dissociates, decomposes, becomes neutralized, or is otherwise transformed to allow the catalyst to facilitate cross-linking of the precursors into solid dielectric materials. Methods for fabricating dielectric materials using such protected catalysts as well as devices comprising the resulting materials are also described. Dielectric materials comprising cross-linked cyclic carbosilane units having a ring structure including C and Si may be formed in this manner.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, David J. Michalak, Jessica M. Torres, Marie Krysak, Jeffery D. Bielefeld
  • Publication number: 20220229364
    Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Marie KRYSAK, James M. BLACKWELL, Robert L. BRISTOL, Florian GSTREIN
  • Publication number: 20220216065
    Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Robert L. BRISTOL, Marie KRYSAK, James M. BLACKWELL, Florian GSTREIN, Kent N. FRASURE
  • Patent number: 11373950
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20220199540
    Abstract: Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Gurpreet Singh, Eungnak Han, Xuanxuan Chen, Tayseer Mahdi, Marie Krysak, Brandon Jay Holybee, Florian Gstrein
  • Publication number: 20220199462
    Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.
    Type: Application
    Filed: October 27, 2021
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Gurpreet Singh, Florian Gstrein, Eungnak Han, Marie Krysak, Tayseer Mahdi, Xuanxuan Chen, Brandon Jay Holybee
  • Patent number: 11320734
    Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Marie Krysak, James M. Blackwell, Robert L. Bristol, Florian Gstrein
  • Publication number: 20220130719
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Inventors: Kevin L. LIN, Robert L. BRISTOL, James M. BLACKWELL, Rami HOURANI, Marie KRYSAK
  • Patent number: 11315798
    Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Marie Krysak, James M. Blackwell, Florian Gstrein, Kent N. Frasure
  • Publication number: 20220093399
    Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventors: Marie KRYSAK, Florian GSTREIN, Manish CHANDHOK
  • Patent number: 11262654
    Abstract: Chain scission resist compositions suitable for EUV lithography applications may include monomer functional groups that improve the kinetics and/or thermodynamics of the scission mechanism. Chain scission resists may include monomer functional groups that reduce the risk that leaving groups generated through the scission mechanism may chemically corrode processing equipment.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Lauren Doyle, Marie Krysak, Patrick Theofanis, James Blackwell, Eungnak Han