Patents by Inventor Marie Zhang

Marie Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240261442
    Abstract: This invention relates to a method to assess nodal disease by magnetic resonance imaging with a contrast agent. The contrast agent comprises biofunctional magnetic nanoparticles coated with polymers outside the iron core and conjugated with antibodies specific to the tumor type to be assessed. Images produced from this magnetic resonance imaging with a contrast agent show heterogenous hypo intensity or heterogenous architecture in regions where binding by the antibodies is present.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 8, 2024
    Applicant: Imagion Biosystems, Inc.
    Inventors: Robert PROULX, Yalia JAYALAKSHMI, Marie ZHANG, Natalie YANG, Wing Fai LAU
  • Publication number: 20230270891
    Abstract: Liposomes have been used in technologies in biological, pharmaceutical, medical and nutritional applications because they can offer biocompatibility, biodegradability, reduced toxicity, and capacity for size and surface modifications. Traditionally, liposomes are prepared by multiple steps. However, multiple steps of preparation may cause a number of problems including low yield, high polydispersity, and poor morphology. Here, we synthesized liposomes containing magnetic iron oxide nanoparticle using one-pot, single step synthesis under ultra-sonication. We optimized the lipid compositions, sonication power, concentration of iron oxide nanoparticles, and antibody conjugation using Cu-free click chemistry. Furthermore, we incorporated doxorubicin inside magnetic liposomes for combined antibody targeting and magnetic guidance. Fluorescence imaging and quantification confirmed that antibody conjugated magnetic liposome showed high cell specific targeting that was enhanced by magnetic delivery.
    Type: Application
    Filed: March 3, 2023
    Publication date: August 31, 2023
    Inventors: Konstantin Sokolov, Marie Zhang, Chang Soo Kim, Dmitry Nevozhay, Rebeca Aburto, Ashok Pehere, Lang Pang, John Hazle, Robert Clinton Bast
  • Publication number: 20140038847
    Abstract: In accordance with one aspect of the present invention, screening and culturing devices have been developed which are useful for the identification of media which support cell viability, growth and/or proliferation, and transformation and/or differentiation. In a further aspect, screening and culturing methods employing the invention screening and culturing devices have been developed. In a still further aspect, methods for making invention screening and culturing devices have been developed.
    Type: Application
    Filed: May 10, 2013
    Publication date: February 6, 2014
    Applicant: Microstem, Inc.
    Inventors: Marie Zhang, Justin Bingham, Naira Serobyan
  • Publication number: 20130303954
    Abstract: Build-in and portable oral hygiene systems and devices are disclosed which systems and devices effectively function without electricity, batteries, mechanical pumps and motors. Build-in oral hygiene systems may utilize a single set of hot and cold water supply hoses and may be integrated with the faucet as a permanent sink apparatus while portable hygiene devices are manpowered and thus may be used at anytime and anywhere.
    Type: Application
    Filed: July 18, 2013
    Publication date: November 14, 2013
    Inventors: Winston Zhang, Kurt Keller, Mary Zhang
  • Publication number: 20130130376
    Abstract: In accordance with one aspect of the present invention, methods have been developed for identifying compositions which support the culture of defined cell populations. In accordance with another aspect of the present invention, methods have been developed for identifying compositions which promote differentiation of defined cell populations. In accordance with yet another aspect of the present invention, methods have been developed for identifying compositions which induce apoptosis of defined cell populations. In accordance with still another aspect of the present invention, methods have been developed for identifying compositions which promote cell senescence of defined cell populations. In accordance with still another aspect of the present invention, methods have been developed for identifying media which modulate the retardation of cell growth of defined cell subpopulation(s).
    Type: Application
    Filed: May 2, 2011
    Publication date: May 23, 2013
    Inventors: Naira Serobyan, Justin Bingham, Marie Zhang
  • Patent number: 7203923
    Abstract: Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on which various components are realized. Depending on the use of an integrated capacitor, micro capacitors can be formed between one introduced layer and the ground layer or between two introduced layers. As all micro capacitors are connected in parallel, an integrated capacitor with usable capacitance is thus produced without occupying an extra space that would otherwise increase the size of the silicon chip. In addition, with proper connections, an interdigitated capacitor can be formed as well.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: April 10, 2007
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Patent number: 7183960
    Abstract: Techniques for designing high-speed integrated circuits are disclosed. According to one aspect of the present invention, an interpolation circuit is disclosed. A method for designing such an interpolation circuit comprises determining an initial value for all resistors in the interpolation circuit, examining whether outputs from the interpolation circuit are evenly spaced across a predefined range of input signals, and when the outputs are not evenly spaced across a predefined range of input signals, adjusting each of the resistors in reference to the outputs so that the outputs are evenly spaced across a predefined range of input signals.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: February 27, 2007
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Publication number: 20060012006
    Abstract: Techniques for producing integrated capacitors are disclosed. According to one of the techniques, one or more layers are introduced in conjunction with a ground layer supporting a substrate on which various components are realized. Depending on the use of an integrated capacitor, micro capacitors can be formed between one introduced layer and the ground layer or between two introduced layers. As all micro capacitors are connected in parallel, an integrated capacitor with usable capacitance is thus produced without occupying an extra space that would otherwise increase the size of the silicon chip. In addition, with proper connections, an interdigitated capacitor can be formed as well.
    Type: Application
    Filed: July 19, 2004
    Publication date: January 19, 2006
    Inventors: John Tung, Minghao (Mary) Zhang
  • Patent number: 6970064
    Abstract: Techniques for implementing transformers with center-taps are described. Based on an overlay winding structure, according to one embodiment, the primary and the secondary of the transformer are respectively formed on two separate layers that are stacked on top of each other, wherein the secondary includes two segments, the two respective terminals of the two segments are coupled together to a component in a circuit to form a center-tap of the secondary. According to another embodiment, three or more separating windings are formed on separate layers. At least one of the windings is a conducting stripe wound in loops and includes a center-tap that extends across but not electrically connected to the loops of the conducting stripe by detouring the conducting stripe through other layers.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: November 29, 2005
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Publication number: 20040195651
    Abstract: Techniques for implementing transformers with center-taps are disclosed. Based on an overlay winding structure, according to one embodiment, the primary and the secondary of the transformer are respectively formed on two separate layers that are stacked on top of each other, wherein the secondary includes two segments, the two respective terminals of the two segments are coupled together to a component in a circuit to form a center-tap of the secondary. According to another embodiment, three or more separating windings are formed on separate layers. At least one of the windings is a conducting stripe wound in loops and includes a center-tap that extends across but not electrically connected to the loops of the conducting stripe by detouring the conducting stripe through other layers.
    Type: Application
    Filed: July 22, 2003
    Publication date: October 7, 2004
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Patent number: 6794978
    Abstract: A structure and method for implementing a precision inductive component within a high frequency integrated circuit is disclosed. The inductive component has a structure of multiple conductive layers dielectrically insulated from each other and located above an integrated circuit substrate. The inductive component comprises a spiral-like inductive layer made of a first conductive layer. Additionally, a number of additional ground planes, each patterned out of its own selected conductive layer to minimize an induced eddy current therein thus improving Q (quality factor) under high frequency operation, are employed with either a linear or a rotational offset amongst them to effect a corresponding amount of adjustment of an inductance value of the inductive component. A number of specific design cases are presented with their respective inductance and RF performance parameters.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: September 21, 2004
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Publication number: 20040113737
    Abstract: Techniques for integrating multiple transformers are disclosed. Although they can be used in other areas, the techniques are particularly suitable in integrated circuits that are demanded to be of small in size. Several winding configurations of transformers are described and all are designed to not occupy multiple individual silicon spaces that would otherwise be occupied by the multiple transformers. Further, without the multiple individual silicon spaces for the transformers, the parasitic effects that would be otherwise introduced by the transformers in the multiple individual silicon spaces will be minimized. As a result, an integrated circuit chip employing transformers implemented in accordance with one of the techniques can accommodate much higher signal frequency, and have smaller size, thus the cost of the integrated circuit chip can be substantially reduced.
    Type: Application
    Filed: July 22, 2003
    Publication date: June 17, 2004
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Patent number: 6683480
    Abstract: It is well known that the parasitic effects in individual components can introduce artifacts into signals when the frequency of the signals exceeds a certain range. Techniques are described to utilize the parasitic effects in favor to the signals by systematically adjusting the components such that the artifacts are minimized. According to one embodiment, a parameter defined as an Electrically Equivalent Geometry or EEG is defined as a function of width and length that confines one part of a transistor controlling how much current can go through. A proper adjustment of the EEG for each of the transistors in a differential amplifier or circuit can reduce the parasitic effects that can cause the artifacts to the signal but also form inherently resonant filtering functions that minimize harmonic components in the output signals.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 27, 2004
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Publication number: 20030214378
    Abstract: A structure and method for implementing a precision inductive component within a high frequency integrated circuit is disclosed. The inductive component has a structure of multiple conductive layers dielectrically insulated from each other and located above an integrated circuit substrate. The inductive component comprises a spiral-like inductive layer made of a first conductive layer. Additionally, a number of additional ground planes, each patterned out of its own selected conductive layer to minimize an induced eddy current therein thus improving Q (quality factor) under high frequency operation, are employed with either a linear or a rotational offset amongst them to effect a corresponding amount of adjustment of an inductance value of the inductive component. A number of specific design cases are presented with their respective inductance and RF performance parameters.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Applicant: Qantec Communication, Inc.
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Publication number: 20030201815
    Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: Qantec Communication, Inc.
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Publication number: 20030189449
    Abstract: It is well known that the parasitic effects in individual components can introduce artifacts into signals when the frequency of the signals exceeds a certain range. Techniques are described to utilize the parasitic effects in favor to the signals by systematically adjusting the components such that the artifacts are minimized. According to one embodiment, a parameter defined as an Electrically Equivalent Geometry or EEG is defined as a function of width and length that confines one part of a transistor controlling how much current can go through. A proper adjustment of the EEG for each of the transistors in a differential amplifier or circuit can reduce the parasitic effects that can cause the artifacts to the signal but also form inherently resonant filtering functions that minimize harmonic components in the output signals.
    Type: Application
    Filed: December 20, 2002
    Publication date: October 9, 2003
    Inventors: Minghao (Mary) Zhang, John C. Tung
  • Patent number: 6556056
    Abstract: A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Silicon On Insulator (SOI) CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another SOI CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting drastic improvement of output signal ripple is also graphically presented.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: April 29, 2003
    Assignee: Qantec Communications, Inc.
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Publication number: 20030052720
    Abstract: A D-type latch with current mode switching using MOS transistors for high speed data communication without excessive noise and poor waveform jittering and a method of quantitative circuit design of such D-type latch circuit is presented. With this method, a value of electrically equivalent channel geometry is selected for the input pair of MOS transistors and a different value of electrically equivalent channel geometry is selected for the feedback pair of MOS transistors so as to reduce the resulting amount of output signal ringing as compared to a similar D-type latch circuit where the corresponding values of electrically equivalent channel geometry are equal. Furthermore, a set of output signal waveforms from a divide-by-2 counter and a divide-by-16 counter using the D-type latch as their building block are presented.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 20, 2003
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Publication number: 20030048117
    Abstract: A method of designing an electronic circuit system with multiple CMOS transistors is presented. With this method, the circuit parameters of the various CMOS transistors as well as the passive electrical components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC (Integrated Circuit) that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The high quality of the resulting output signals from each divider stage is graphically presented. In another embodiment, the method is applied to a CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The high quality of the resulting output signal is also graphically presented.
    Type: Application
    Filed: May 2, 2002
    Publication date: March 13, 2003
    Applicant: Qantec Communication, Inc.
    Inventors: John C. Tung, Minghao (Mary) Zhang
  • Patent number: 6459308
    Abstract: A method of designing an electronic circuit system with multiple Bipolar transistor is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Bipolar IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another Bipolar IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting improvement of output signal ripple is also graphically presented.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: October 1, 2002
    Assignee: Qantec Communication, Inc.
    Inventors: John C. Tung, Minghao Mary Zhang