Patents by Inventor Marika NAKAMURA

Marika NAKAMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982919
    Abstract: It is an object of the present invention to provide a technique for making it possible to reduce the size of a Mach-Zehnder type optical modulator. In a clad layer, provided are a plurality of first and second via holes along an optical waveguide. The Mach-Zehnder type optical modulator includes a first travelling wave electrode connected to a first semiconductor region through the plurality of first via holes, extending along the optical waveguide in a plan view to have a width which is wider and a length and a second travelling wave electrode connected to a second semiconductor region through the plurality of second via holes, extending along the optical waveguide in a plan view to have a width which is wider and a length.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 14, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Marika Nakamura, Shusaku Hayashi, Koichi Akiyama
  • Publication number: 20240136439
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 25, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
  • Publication number: 20230352599
    Abstract: A source layer is provided on a first p-type layer made of a nitride-based semiconductor, and includes a semiconductor region including electrons as carriers. A drain layer faces the source layer in a first direction on the first p-type layer with a gap being provided therebetween, and includes a semiconductor region including electrons as carriers. A channel structure is provided between the source layer and the drain layer on the first p-type layer, in which a channel region and a gate region are alternately disposed in a second direction perpendicular to the first direction. A channel layer included in the channel structure forms at least a part of the channel region, and is made of a nitride-based semiconductor. A gate layer included in the channel structure forms at least a part of the gate region, and electrically connects a gate electrode and the first p-type layer.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 2, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hisashi SAITO, Yuki TAKIGUCHI, Shigeyoshi USAMI, Takahiro YAMADA, Marika NAKAMURA, Eiji YAGYU
  • Publication number: 20230143585
    Abstract: A first nitride semiconductor layer and a second nitride semiconductor layer are laminated in a first direction. The first and second nitride semiconductor layers form a heterojunction, and a two-dimensional carrier gas is induced in the first nitride semiconductor layer. A drain electrode is opposite to a source electrode via gate electrode in a third direction. The source electrode and the drain electrode conduct with the first nitride semiconductor layer. The first and second nitride semiconductor layers form a Schottky junction with the gate electrode. A first layer is located between the gate electrode and the drain electrode in the third direction and is in contact with the gate electrode, and is in contact with the second nitride semiconductor layer in a second direction. The first layer suppresses induction of the two-dimensional carrier gas in the first nitride semiconductor layer opposite to the first layer in the first direction.
    Type: Application
    Filed: May 21, 2021
    Publication date: May 11, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Marika NAKAMURA, Shigeyoshi USAMI, Yuki TAKIGUCHI, Takahiro YAMADA, Hisashi SAITO, Tatsuro WATAHIKI, Eiji YAGYU
  • Publication number: 20210341813
    Abstract: It is an object of the present invention to provide a technique for making it possible to reduce the size of a Mach-Zehnder type optical modulator. In a clad layer, provided are a plurality of first and second via holes along an optical waveguide. The Mach-Zehnder type optical modulator includes a first travelling wave electrode connected to a first semiconductor region through the plurality of first via holes, extending along the optical waveguide in a plan view to have a width which is wider and a length and a second travelling wave electrode connected to a second semiconductor region through the plurality of second via holes, extending along the optical waveguide in a plan view to have a width which is wider and a length.
    Type: Application
    Filed: December 6, 2018
    Publication date: November 4, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Marika NAKAMURA, Shusaku HAYASHI, Koichi AKIYAMA
  • Publication number: 20150228756
    Abstract: A semiconductor device includes an Alx1Ga1-x1N (0?x1?1) barrier layer, and a gate electrode that is disposed on a surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, forms a Schottky junction with the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, and has an Ni single-layer structure. Annealing processing is performed with respect to the gate electrode at a temperature of 500° C. or above under a nitrogen atmosphere to form a reaction layer between the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer and the gate electrode.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 13, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichiro KURAHASHI, Takuma Nanjo, Muneyoshi Suita, Yosuke Suzuki, Akifumi Imai, Marika Nakamura, Eiji Yagyu
  • Publication number: 20150069408
    Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 12, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuma NANJO, Akifumi IMAI, Yosuke SUZUKI, Muneyoshi SUITA, Kenichiro KURAHASHI, Marika NAKAMURA, Eiji YAGYU