Abstract: A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the bit line selection signal supplied to the selection circuits. A global bit line selection signal line is connected to the control circuit, and receives the bit line section signal therefrom. Drive circuits, input portions of which are connected to the global bit line selection signal line, drive the bit line selection signal supplied to the global bit line selection signal line and output it, and the drive circuits are arranged within the sense amplifier bank. A local bit line selection signal line supplies the bit line selection signal driven by the drive circuit to the selection circuit.

Abstract: In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side of the data control unit through a first local data line, and the second memory block is connected to the other side of the data control unit through a second local data line.

Abstract: In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side of the data control unit through a first local data line, and the second memory block is connected to the other side of the data control unit through a second local data line.

Abstract: A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the bit line selection signal supplied to the selection circuits. A global bit line selection signal line is connected to the control circuit, and receives the bit line section signal therefrom. Drive circuits, input portions of which are connected to the global bit line selection signal line, drive the bit line selection signal supplied to the global bit line selection signal line and output it, and the drive circuits are arranged within the sense amplifier bank. A local bit line selection signal line supplies the bit line selection signal driven by the drive circuit to the selection circuit.

Abstract: A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate 11, and pads 13 stacked thereon via an insulation film 12. A particular pad 13a is connected to a signal wiring 17a formed in a bus line region 17, and a capacitor-forming conductor 14 behaving as an impedance adjusting conductor is formed to surround the pad 13a. A source line conductor 15 is made in a space between the pad 13a and the capacitor-forming conductor 14 to encircle the capacitor-forming conductor 14. Therefore, the pad capacitance can be increased by using the space around the pad 13a, other signal wirings 17b and any others formed in the bus line region 17 are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Abstract: A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate 11, and pads 13 stacked thereon via an insulation film 12. A particular pad 13a is connected to a signal wiring 17a formed in a bus line region 17, and a capacitor-forming conductor 14 behaving as an impedance adjusting conductor is formed to surround the pad 13a. A source line conductor 15 is made in a space between the pad 13a and the capacitor-forming conductor 14 to encircle the capacitor-forming conductor 14. Therefore, the pad capacitance can be increased by using the space around the pad 13a, other signal wirings 17b and any others formed in the bus line region 17 are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Abstract: To provide a semiconductor memory for synchronizing input of a command except for POWER-DOWN-EXIT or the like and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having this external clock as a trigger and after activation of a column system circuit, using the internal operation synchronous pulse as a trigger. This semiconductor memory uses column pulse transfer signals, which are different between read and write to control a column system circuit.