Abstract: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.

Abstract: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.

Abstract: A distributed shared memory system includes a plurality of nodes. Each of the nodes includes a plurality of shared multiprocessors. Each of the shared multiprocessors includes a processor, a shared cache, and a memory. Each of the nodes includes a coherence maintaining unit that maintains cache coherence based on a plurality of directories each of which corresponding to each of the shared caches included in the distributed shared memory system.

Abstract: A performance simulation apparatus that simulates operations of a computer, and collects and displays data that relates to dynamic conditions of hardware elements of the computer includes a graphic-data creating unit that creates graphic data for graphically displaying relationships between the dynamic conditions of the hardware elements; and a graphic-data displaying unit that displays the dynamic conditions of the hardware elements by using the graphic data that is created by the graphic-data creating unit.

Abstract: A command detector detects a control command based on voice input through a telephone or a door phone or the like, and a user and control command identifying section identifies the user and the control command. A command controller decides execution of the control command based on a comparison between a security level set to the control command and to an authority level and a priority level set to the user.

Abstract: A command detector detects a control command based on voice input through a telephone or a door phone or the like, and a user and control command identifying section identifies the user and the control command. A command controller decides execution of the control command based on a comparison between a security level set to the control command and to an authority level and a priority level set to the user.

Abstract: The memory access arithmetic operation instruction is executed in the data processing apparatus including a memory access pipeline and arithmetic operation pipeline. The decoding and development of the memory access arithmetic operation are carried out after the memory access arithmetic operation instruction is input to the memory access pipeline and the memory access results and the memory access arithmetic instruction are output to the arithmetic operation pipeline.

Abstract: The memory access arithmetic operation instruction is executed in the data processing apparatus including a memory access pipeline and arithmetic operation pipeline. The decoding and development of the memory access arithmetic operation are carried out after the memory access arithmetic operation instruction is input to the memory access pipeline and the memory access results and the memory access arithmetic instruction are output to the arithmetic operation pipeline.