Patents by Inventor Mariko Takagi

Mariko Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10562006
    Abstract: The purpose of the present invention is to provide a particulate water absorbing agent having both a high water absorption multiplying factor and a high water absorption rate and a method for manufacturing the same. The present invention is a particulate water absorbing agent for which CRC is 30 to 50 g/g, wherein the weight average particulate diameter (D50) is 200-600 ?m, and the DRC index given by the following formula is a specific value (for example, 43, 30, or 20) or less: DRC index=(49?DRC5min [g/g])/(D50 [?m]/1000).
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: February 18, 2020
    Assignee: NIPPON SHOKUBAI CO., LTD.
    Inventors: Kazushi Torii, Mariko Tamaki, Daisuke Takagi, Yuichiro Horimoto, Taishi Kobayashi, Taku Fujimoto, Takahiro Kitano, Taku Iwamura, Hiroki Kawada, Hiroyuki Goto, Yasuhisa Nakajima, Hiroyuki Ikeuchi
  • Publication number: 20140374355
    Abstract: There is disclosed a pretreatment device for membrane separation including a honeycomb structure having porous partition walls with which a plurality of cells extending from one end surface to the other end surface are formed to become through channels of a fluid, and a storage container in which the honeycomb structure is stored and which has an inflow port and an outflow port of the fluid, and the partition walls include an adsorbent as a main component, a membrane-like adsorbent is disposed on the surfaces of the partition walls, or the partition walls include the adsorbent as the main component and the membrane-like adsorbent is disposed on the surfaces of the partition walls. The pretreatment device for membrane separation is disclosed in which impurities in the fluid to be treated which influence (adversely affect) a separation membrane are efficiently adsorbed, to enable suppression of deterioration of the separation membrane.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Inventor: Mariko TAKAGI
  • Patent number: 8764889
    Abstract: There is provided a silica membrane filter having performance of selectively separating an aromatic compound and performance of selectively separating an alcohol. The silica membrane filter is provided with a porous substrate and a silica membrane. The ratio of a He gas permeation amount to an N2 gas permeation amount (He gas permeation amount/N2 gas permeation amount) is 7 or less, and the ratio of the N2 gas permeation amount to a SF6 gas permeation amount (N2 gas permeation amount/SF6 gas permeation amount) is 1.5 or more.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 1, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Mariko Takagi, Kenichi Noda, Nobuhiko Mori, Masaaki Kawai, Aya Satoh
  • Patent number: 7638432
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20070194382
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 23, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 7220672
    Abstract: The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffusion layer. The silicide film is thicker on the gate electrode than on the source-drain diffusion layer. The manufacturing method comprises forming a gate electrode on a gate insulating film, followed by forming a source-drain diffusion layer. Then, atoms inhibiting a silicidation are selectively introduced into the source-drain diffusion layer, and a high melting point metal film is formed on the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into silicide films selectively on the gate electrode and the source-drain diffusion layer.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20050158958
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: February 8, 2005
    Publication date: July 21, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 6869867
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: March 22, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Publication number: 20030001218
    Abstract: A gate insulating film is formed of an oxynitride film prepared by adding nitrogen atoms to a thermal oxide film. The Si—N bonds each having a second adjacent oxygen atom as viewed on the basis of the nitrogen atom within the oxynitride film are positioned at least one atomic layer inside the interface between the silicon substrate and the oxynitride film to allow the gate insulating film to prevent boron atoms contained in the gate electrode from being migrated through the gate insulating film without lowering the driving force of the transistor.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 2, 2003
    Inventor: Mariko Takagi
  • Patent number: 6362511
    Abstract: In A MIS type semiconductor device using a polycrystalline silicon film as a gate electrode, a lower portion of the polycrystalline silicon film has larger grains in average diameter than an upper portion thereof, and there is no peak of oxygen concentration in a film thickness direction in the polycrystalline silicon film.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: March 26, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Mariko Takagi
  • Publication number: 20010045605
    Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.
    Type: Application
    Filed: July 30, 2001
    Publication date: November 29, 2001
    Inventors: Katsura Miyashita, Hisao Yoshimura, Mariko Takagi
  • Patent number: 6169019
    Abstract: In a method of manufacturing a semiconductor device, a titanium silicide layer is formed on a region of a diffusion layer formed in a semiconductor substrate. A silicon nitride film functioning as an etching stopper is formed on the semiconductor substrate. The silicon nitride film covers the layer. An interlayered insulating film is formed on the silicon nitride film. A barrier metal of Tin/Ti is formed in a contact hole, which is formed in the interlayered insulating film. The contact holes is opened toward the diffusion layer. A conductive film comprising a Ti—Si—N based alloy is formed between a metal wiring and the diffusion layer. The conductive film is formed by reacting the silicon nitride film with titanium contained in the titanium silicide layer or the barrier metal. With these manufacturing features, the manufacturing process is not increased and the manufacturing cost can be reduced.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: January 2, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mariko Takagi
  • Patent number: 5929505
    Abstract: A first electrode layer is formed on a semiconductor substrate, and surfaces other than a top surface thereof are buried in an insulation film, and the top surface makes the same surface as that of the insulation film. An antifuse insulation film is formed on a flat surface including the top surface of the first electrode layer. A second electrode layer is formed on the antifuse insulation film. An antifuse portion is formed by self-alignment at a cross point between the first and second electrode layers.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Takagi, Ichiro Yoshii
  • Patent number: 5866938
    Abstract: A semi conductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Takagi, Ichiro Yoshii, Kaoru Hama, Naoki Ikeda, Hiroaki Yasuda
  • Patent number: 5682059
    Abstract: In a semiconductor device including an anti-fuse element, a first electrode layer is formed on a semiconductor substrate. A first insulating layer is formed only on the first electrode layer for insulating the first electrode layer. An anti-fuse insulating film is coated on at least one side wall portion of each of the first electrode layer and the first insulating layer. A second electrode layer is formed on the anti-fuse insulating film, and the first and second electrode layers and the anti-fuse insulating film constitute the anti-fuse element.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: October 28, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Yoshii, Mariko Takagi
  • Patent number: 5625219
    Abstract: A programmable device uses anti-fuse elements. The device has a wiring layer on an insulator film on a semiconductor substrate, and it is programmed by connected condition of this wiring. The wiring is separated, such as a first wiring line and a second wiring line on the same plane, beforehand so has been disconnected at separated nodes. A thin insulator film is formed on the disconnection nodes at least, and a further floating electrode, consisting of an aluminum alloy, is formed on the thin insulator film, so that an anti-fuse element is formed straddling the first and the second wiring. When it is programmed, in order to change the disconnected anti-fuse element into a conductive state, a destructive electric potential difference is impressed between the first and the second wiring lines through the thin insulator film. As a result, the thin insulator film is broken, so that the first and the second wiring lines are connected with the floating electrode.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: April 29, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mariko Takagi
  • Patent number: 5550400
    Abstract: A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: August 27, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Takagi, Ichiro Yoshii, Kaoru Hama, Naoki Ikeda, Hiroaki Yasuda