Patents by Inventor Marilyn I. Wright

Marilyn I. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7262864
    Abstract: A test structure includes a first plurality of lines and a second plurality of lines intersecting the first plurality of lines. The first and second pluralities of lines defining a grid having openings. A method for determining grid dimensions includes providing a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings; illuminating at least a portion of the grid with a light source; measuring light reflected from the illuminated portion of the grid to generate a reflection profile; and determining a dimension of the grid based on the reflection profile. A metrology tool is adapted to receive a wafer having a test structure comprising a plurality of intersecting lines that define a grid having openings. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grid.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Kevin R. Lensing, J. Broc Stirton, Marilyn I. Wright
  • Patent number: 7109101
    Abstract: In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In one embodiment useful to 248 nm and 193 nm photolithography exposure wavelengths, amorphous carbon is plasma-deposited on a substrate to pre-defined thickness and pre-defined optical properties. A SiON layer is combined with a silicon-rich oxide layer, a silicon-rich nitride layer or a TEOS layer to create a capping layer resistant to species-migration. Layers are formulated to pre-determined thicknesses, refractive indices and extinction coefficients. The capping stacks constitute an effective etch mask for the amorphous carbon; and the hardmask properties of the amorphous carbon are not compromised. The disclosure has immediate application to fabricating polysilicon gates.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: September 19, 2006
    Assignees: AMD, Inc., Motorola, Inc.
    Inventors: Marilyn I. Wright, Srikanteswara Dakshina-Murthy, Kurt H. Junker, Kyle Patterson
  • Patent number: 6913958
    Abstract: In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 5, 2005
    Assignee: Advanced Micro Devices
    Inventors: Marina V. Plat, Marilyn I. Wright, Chih Yuh Yang, Douglas J. Bonser
  • Patent number: 6900002
    Abstract: An amorphous carbon layer of an antireflective bi-layer hardmask is processed to increase its density prior to patterning of an underlying polysilicon layer using the bi-layer hardmask. The increased density of the layer increases its resistance to polysilicon etch chemistry, thus reducing the likelihood of patterning inaccuracies resulting from amorphous carbon depletion during polysilicon etch, and enabling the patterning of thicker polysilicon layers than can be reliably patterned without densification. The increased density also reduces stresses, thus reducing the likelihood of delamination. Densification may be performed by UV or e-beam irradiation after formation of an overlying protective layer. Densification may also be performed by annealing the amorphous carbon layer in situ prior to formation of the overlying protective layer. In the latter case, annealing reduces the amount of outgassing that occurs during formation of the protective layer, thus reducing the formation of pin holes.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 31, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marina V. Plat, Marilyn I. Wright, Lu You, Scott A. Bell
  • Patent number: 6893967
    Abstract: A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 17, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marilyn I. Wright, Douglas J. Bonser, Lu You, Kay Hellig
  • Patent number: 6864556
    Abstract: A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 8, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lu You, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Richard J. Huang, Christopher F. Lyons, Mark S. Chang, Marilyn I. Wright
  • Patent number: 6804014
    Abstract: A test structure includes a plurality of lines and a plurality of contact openings defined in the lines. A method for determining contact opening dimensions includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: October 12, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Kevin R. Lensing, J. Broc Stirton, Marilyn I. Wright
  • Patent number: 6774998
    Abstract: A method includes providing a wafer having a first grating structure and a second grating structure formed in a photoresist layer. At least a portion of the first and second grating structures is illuminated with a light source. Light reflected from the illuminated portion of the first and second grating structures is measured to generate a reflection profile. Misregistration between the first and second grating structures is determined based on the reflection profile. A processing line includes a photolithography stepper, a metrology tool, and a controller. The photolithography stepper is adapted to process wafers in accordance with an operating recipe. The metrology tool is adapted to receive a wafer processed in the stepper. The wafer has a first grating structure and a second grating structure formed in a photoresist layer. The metrology tool includes a light source, a detector, and a data processing unit.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: August 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marilyn I. Wright, Kevin R. Lensing, James Broc Stirton
  • Patent number: 6773939
    Abstract: A method for determining critical dimension variation includes providing a wafer having a grating structure comprising a plurality of lines; illuminating at least a portion of the lines with a light source; measuring light reflected from the illuminated portion of the lines to generate a reflection profile; and determining a critical dimension variation measurement of the lines based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure comprising a plurality of lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the lines. The detector is adapted to measure light reflected from the illuminated portion of the lines to generate a reflection profile. The data processing unit is adapted to determine a critical dimension variation measurement of the lines based on the reflection profile.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: August 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Marilyn I. Wright
  • Patent number: 6766215
    Abstract: A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin R. Lensing, Marilyn I. Wright
  • Patent number: 6764949
    Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Darin Chan, Philip A. Fisher, Christopher F. Lyons, Mark S. Chang, Pei-Yuan Gao, Marilyn I. Wright, Lu You, Srikanteswara Dakshina-Murthy
  • Patent number: 6764947
    Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darin Chan, Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih Yuh Yang, Lu You, Scott A. Bell, Philip A. Fisher
  • Patent number: 6716646
    Abstract: The present invention provides for a method and an apparatus for overlay measurements using optical techniques. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. A scatterometry overlay analysis based upon the metrology data is performed. At least one modified manufacturing parameter is calculated based upon the scatterometry overlay analysis.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marilyn I. Wright, Kevin R. Lensing, James Broc Stirton, Richard J. Markle
  • Patent number: 6697153
    Abstract: A method and an apparatus for analyzing line structures during semiconductor wafer processing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Film property data from the semiconductor wafer is acquired. Data from a reference library is accessed; the data comprising optical data relating to a line structure formation on a semiconductor wafer, based upon the film property data. The metrology data is compared to data from the reference library. A line structure fault detection analysis is performed in response to the comparison of the metrology data and the reference library data.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: February 24, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marilyn I. Wright, James B. Stirton
  • Publication number: 20040023475
    Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.
    Type: Application
    Filed: December 30, 2002
    Publication date: February 5, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Marina V. Plat, Chih Yuh Yang, Scott A. Bell, Darin Chan, Philip A. Fisher, Christopher F. Lyons, Mark S. Chang, Pei-Yuan Gao, Marilyn I. Wright, Lu You, Srikanteswara Dakshina-Murthy
  • Patent number: 6657716
    Abstract: A method and an apparatus for detecting a necking error during semiconductor manufacturing. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a poly-silicon formation on a semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: December 2, 2003
    Assignee: Advanced Micro Devices Inc.
    Inventors: Kevin R. Lensing, Marilyn I. Wright
  • Patent number: 6650423
    Abstract: A test structure includes a plurality of trenches and a plurality of columns defined in the trenches. A method for determining column dimensions includes providing a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches; illuminating at least a portion of the columns with a light source; measuring light reflected from the illuminated portion of the columns to generate a reflection profile; and determining a dimension of the columns based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of trenches and a plurality of columns defined in the trenches includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the columns. The detector is adapted to measure light reflected from the illuminated portion of the columns to generate a reflection profile.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: November 18, 2003
    Assignee: Advanced Micro Devices Inc.
    Inventors: Richard J. Markle, Kevin R. Lensing, J. Broc Stirton, Marilyn I. Wright
  • Patent number: 6509201
    Abstract: The present invention provides for a method and an apparatus for characterizing wafer stress. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. Micro-Raman data relating to the processed semiconductor device is acquired. A wafer-stress analysis based upon the metrology data and the micro-Raman data is performed. A feedback process based upon the wafer stress analysis is performed.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Marilyn I. Wright
  • Patent number: 6479309
    Abstract: A method for determining conformality of a process layer includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer overlying the grating structure with a light source; measuring light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile; and determining conformality of the process layer based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure and a process layer formed over the grating structure includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the grating structure and the process layer to generate a reflection profile.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Marilyn I. Wright
  • Patent number: 6458610
    Abstract: A method and an apparatus for performing film stack fault detection. At least one semiconductor wafer is processed. Metrology data from the processed semiconductor wafer is acquired. Data from a reference library comprising optical data relating to a film stack on the semiconductor wafer is accessed. The metrology data is compared to data from the reference library. A fault-detection analysis is performed in response to the comparison of the metrology data and the reference library data.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin R. Lensing, Marilyn I. Wright, James B. Stirton