Abstract: Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty cycle on the access line to enable writing to a first memory cell of the array of memory cells, and the control module is configured to assert a second signal for a read duty cycle on the access line to enable reading from the first memory cell. The write duty cycle and the read duty cycle are each selected from a plurality of possible duty cycles. In an exemplary embodiment, the read duty cycle and the write duty cycle are chosen to optimize a performance parameter for the memory element.