Patents by Inventor Marina M. Medvedeva

Marina M. Medvedeva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7401318
    Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: July 15, 2008
    Assignee: LSI Corporation
    Inventors: Stanislav V. Aleshin, Marina M. Medvedeva, Sergei B. Rodin, Eugeni E. Egorov
  • Patent number: 7039896
    Abstract: The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 2, 2006
    Assignee: LSI Logic Corporation
    Inventors: Marina M. Medvedeva, Stanislav V. Aleshin, Eugeni E. Egorov, Sergei B. Rodin
  • Patent number: 7035446
    Abstract: A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: April 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Marina M. Medvedeva, Jaroslav V. Kalinin, Stanislav V. Aleshin, Nadya Strelkova
  • Patent number: 6988260
    Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 17, 2006
    Assignee: LSI Logic Corporation
    Inventors: Stanislav V. Aleshin, Marina M. Medvedeva, Sergei B. Rodin, Eugeni E. Egorov
  • Patent number: 6934410
    Abstract: Local images of photolithographic masks are assigned to classes based on similarity of functions of circuits formed by the images, so that all of the images of a class can be corrected by correcting one of the members. Boundaries of photolithographic masks are corrected for diffusion of light by moving regions based on process light intensity and proximity of close connections. Boundaries are also corrected for shifting of photoactive material in photoresists by calculating the amount of shift based on light intensities at pattern points.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: August 23, 2005
    Assignee: LSI Logic Corporation
    Inventors: Stanislav V. Aleshin, Marina M. Medvedeva, Eugeni E. Egorov, Gennady V. Belokopytov, Paul G. Filseth
  • Publication number: 20030219154
    Abstract: A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.
    Type: Application
    Filed: May 22, 2002
    Publication date: November 27, 2003
    Inventors: Marina M. Medvedeva, Jaroslav V. Kalinin, Stanislav V. Aleshin, Nadya Strelkova