Patents by Inventor Marina QUINTERO-PÉREZ

Marina QUINTERO-PÉREZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11737377
    Abstract: A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 22, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sebastian Heedt, Marina Quintero-Pérez, Francesco Borsoi, Kevin Alexander Van Hoogdalen, Leonardus Petrus Kouwenhoven
  • Publication number: 20230147168
    Abstract: One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.
    Type: Application
    Filed: March 31, 2020
    Publication date: May 11, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Marina QUINTERO PÉREZ, David Johannes VAN WOERKOM, Vinay Kumar CHINNI, Amrita SINGH
  • Publication number: 20230128554
    Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component and a superconductor component arranged over the semiconductor component. The superconductor component comprises a continuous portion of a superconductor material and a discontinuous portion of a non-ferromagnetic metal. The discontinuous portion is configured to increase the critical field of the superconductor component. It has been found that providing a superconductor component with a discontinuous portion of non-ferromagnetic metal may increase the critical field of the superconductor component, allowing the device to be operated in a stronger magnetic field. Further aspects provide a method of fabricating the device, and the use of a non-ferromagnetic metal to increase the critical field of a superconductor component of a semiconductor-superconductor hybrid device.
    Type: Application
    Filed: February 28, 2020
    Publication date: April 27, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Marina QUINTERO PÉREZ, Grzegorz Piotr MAZUR, Nick VAN LOO
  • Publication number: 20220149261
    Abstract: A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.
    Type: Application
    Filed: February 15, 2019
    Publication date: May 12, 2022
    Applicants: Microsoft Technology Licensing, LLC, Delft University of Technology
    Inventors: Sebastian HEEDT, Marina QUINTERO-PÉREZ, Francesco BORSOI, Kevin Alexander VAN HOOGDALEN, Leonardus Petrus KOUWENHOVEN