Abstract: A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor in a second active area. A multilayer structure is deposited, comprising a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer. The multilayer structure is defined to form two bands, the first band defining gate regions of the byte selection transistor and the cell selection transistor, and the second band defining the gate region of the floating gate transistor. A portion of the first band extends over a portion of insulating layer adjacent to the byte selection transistor. An opening is formed in the portion of the first band, exposing the first polysilicon layer, and a conductive layer is formed in the opening, electrically coupling the first polysilicon layer with the second polysilicon layer.

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection

Abstract: In a matrix of non volatile memory cells integrated on a semiconductor substrate, each memory cell includes a floating gate transistor and a selection transistor formed in a first active area, while each byte includes a byte selection transistor formed in a second active area separated from the first by portions of insulating layer. A portion of a multilayer structure including a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer extends over the byte selection and selection transistors, forming the gate regions thereof, and further extending on a portion of insulating layer. A conductive layer is formed in an opening in the second polysilicon and dielectric layers, over the portion of insulating layer, putting the first polysilicon layer in electric contact with the second polysilicon layer. Another portion of the multiplayer structure comprises the gate region of the floating gate transistor.

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection