Patents by Inventor Marina Vroubel

Marina Vroubel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532546
    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 20, 2022
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Bartholomeus Wilhelmus Christiaan Hovens, Marina Vroubel
  • Publication number: 20220344257
    Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 27, 2022
    Inventors: Viet Thanh Dinh, Bartholomeus Wilhelmus Christiaan Hovens, Marina Vroubel
  • Patent number: 10580906
    Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 3, 2020
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Marina Vroubel, Paul Alexander Grudowski