Abstract: A process that incorporates teachings of the subject disclosure may include, for example, providing a first silicon dioxide layer on the silicon substrate, depositing a modifier layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide and annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide. The annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates. The first and second silicon dioxide layers have thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide. Other embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: A method that incorporates teachings of the subject disclosure may comprise, for example, selecting a barium-strontium-titanate (BST) material, wherein the BST material has a perovskite lattice structure with at least a first lattice constant and a second lattice constant; selecting a strontium-barium-niobate (SBN) material, wherein the SBN material has a lattice structure with at least a third lattice constant and a fourth lattice constant, wherein the third lattice constant is substantially equal to the first lattice constant, and wherein the fourth lattice constant is substantially equal to the second lattice constant; and growing, on a grain boundary region of the BST material, the SBN material, wherein the growing is via self-assembly, and wherein the growing is facilitated by the third lattice constant of the SBN material being substantially equal to the first lattice constant and the fourth lattice constant of the SBN material being substantially equal to the second lattice constant.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents (by a process including vacuum annealing and hot-pressing) to provide a sputtering target. Other embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor a silicon substrate having a silicon dioxide layer; an adhesion layer on the silicon dioxide layer, wherein the adhesion layer is a polar dielectric; a first electrode layer on the adhesion layer; a dielectric layer on the first electrode layer; and a second electrode layer on the dielectric layer. Other embodiments are disclosed.

Abstract: A process that incorporates teachings of the subject disclosure may include, for example, providing a first silicon dioxide layer on the silicon substrate, depositing a modifier layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide and annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide. The annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates. The first and second silicon dioxide layers have thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide. Other embodiments are disclosed.

Abstract: A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents (by a process including vacuum annealing and hot-pressing) to provide a sputtering target. Other embodiments are disclosed.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.

Abstract: A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.

Abstract: A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a thin film capacitor having a substrate, a first electrode layer on the substrate, a first dielectric layer on the first electrode layer where the first dielectric layer has a columnar-oriented grain structure, a group of second dielectric layers stacked on the first dielectric layer where each of the group of second dielectric layers has a randomly-oriented grain structure, and a second electrode layer on the group of second dielectric layers. Other embodiments are disclosed.

Abstract: A tunable capacitor that incorporates teachings of the subject disclosure may include: a substrate; a first dielectric layer over the substrate; a plurality of bias lines encapsulated between the substrate and the tunable dielectric layer; a first metal layer over the tunable dielectric layer (wherein the first metal layer has a plurality of first gaps); an upper bias layer over the first metal layer (herein each of a plurality of portions of the upper bias layer extend through a respective one of the plurality of first gaps to come into contact with the first dielectric layer, and wherein at least a second gap is disposed in the upper bias layer); and a second metal layer (wherein a portion of the second metal layer extends through the second gap to come into contact with the first metal layer). Other embodiments are disclosed.

Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a fabricated thin film capacitor formed by depositing a first dielectric layer on a first electrode layer utilizing a first process that is performed at a first temperature, depositing a second dielectric layer on the first dielectric layer utilizing a second process that forms a randomly-oriented grain structure for the second dielectric layer, depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a second temperature and that forms a columnar-oriented grain structure for the third dielectric layer where the second temperature is higher than the first temperature, and depositing a second electrode layer on the third dielectric layer to form the thin film capacitor. Other embodiments are disclosed.