Abstract: Camera systems are often built up from a base station, a detachable cable, and a camera. A dangerous situation may arise the moment the cable is detached from the camera because there is (still) a voltage present on the cable. The invention provides a camera system in which this problem is solved by means of a safety circuit capable of detecting from the base station whether a camera is connected to the cable or not.

Abstract: Camera systems are often built up from a base station, a detachable cable, and a camera.

Abstract: A motor control device controls an electric 3-phase brushless d.c. motor (10) having a magnetic rotor (15) and three windings (11, 12, 13). The motor control device includes a detection unit (20) adapted to generate a commutation signal (21) on the basis of the back-emf voltage produced in the windings (11, 12 and 13). The motor control device further includes an output stage (30) having a first terminal (31) and a second terminal (32) for the connection of a power-supply source, outputs (33, 34, 35) for the connection of the windings (11, 12 and 13) and a number of semiconductor elements (36) for selectively coupling the terminals (31, 32) to the outputs (33, 34, 35) in dependence upon the commutation signal (21). The motor control device further includes a phase detector (40) adapted to generate a phase-error signal (43) which is representative of the phase difference between a sensor signal and a reference signal.

Abstract: In a sampling circuit including a first main terminal (P) and a series coupling of a hold capacitor (C2) and a sampling switch (S2) between the first main terminal (P) and a second main terminal (E), a parallel circuit (L2, R4) of a coil and a resistor (L2) is coupled in series with the sampling switch (S2) and the hold capacitor (C2), whereby the combination of the coil (L2), the resistor (R4) and the hold capacitor (C2) generate an excitation within a time period in which the sampling switch (S2) is conductive.

Abstract: A switched voltage converter formed asymmetrically or symmetrically with one (S1) or two controlled semiconductor switches, respectively, connected in a series arrangement, with a first coil (L1) and a first semiconductor switching element (D1), for example, a diode. The coil is connected to a terminal of a first (C1) and a second (C2) capacitor. Arranged in parallel with the switch (S1) is a series arrangement of the first capacitor (C1) and of the parallel arrangement consisting of a second coil (L2) and a second diode (D2) in series and of a third diode (D3) and a third capacitor (C3) also in series. The junction point of the third diode (D3) and the third capacitor (C3) is connected to the first diode (D1) via a d.c. conection comprising a fourth (D4) and a fifth (D5) diode. The junction point of the fourth (D4) and a fifth (D5) diode is connected via the second capacitor (C2) to the junction point of the first coil (L1) and the first diode (D1).

Abstract: A switched direct voltage converter comprises at least one semiconductor switch (S1) controlled by a control circuit (CC) via a switching input (SI). The semiconductor switch is formed by at least one pair of complementary field effect transistors (T1, T2) connected in a series arrangement (I1) having through-connected voltage-controlled gate electrodes. A converted direct voltage (VS) is obtained by changing over the switch (S1) between first and second supply voltage terminals (VT1, VT2). An input terminal (IT) for connection to a direct voltage supply source (V1) is connected via a coil (L) to a series junction point (SP) between the pair of complementary field effect transistors (T1, T2). A converter output terminal (OT) is connected to one (VT1) of the supply voltage terminals, and a capacitor (C3) is connected between the first and second supply voltage terminals (VT1, VT2) and between the input and output terminals (IT, OT), respectively.

Abstract: In, more specifically, image-processing systems in which images must be stored in a memory (4) of a signal processing arrangement (1) for differential encoding, the memory capacity required is very large. It is possible to save memory capacity by using a square-wave signal generator (12) generating a bit sequence which provides the predictable information which was previously stored in the least significant bit position in the memory (4).

Abstract: A power supply system comprising an a.c. voltage source (ACS), a load (LL) and a detachable (DCC) cable connection (CC). In order to prevent a dangerously high a.c. voltage from occurring between cable conductors (CC1, CC2) when the cable connection is loose, a safety circuit (CITSR) is provided which includes an on/off switching circuit (S1, SR1, S2, SR2). The safety circuit (CITSR) includes a parallel arrangement (CI) of at least one capacitor (C) and a direct current source (I). The parallel arrangement (CI) is part of a direct current circuit (CC2, DC2, CC1, S1, DC1, CC2) which is closed via the cable conductors (CC1, CC2), the a.c. voltage source (ACS) and the load (LL). The parallel arrangement (CI) is coupled to the on/off switching circuit (S1, SR1, S2, SR2) via a threshold circuit (TC). When a controllable a.c.

Abstract: The use of a field interpolation circuit which interpolates by means of equal amplitudes of the information from two successive fields results in a television line standard doubler capable of furnishing a very good picture quality.

Abstract: A hybrid D-PCM transmission system includes a transmitter in which an information signal x(n) is converted into a DPCM signal d(n) and an error reduction circuit in which this information signal x(n), or an estimated version thereof, is quantized and encoded to provide an error reduction signal y(n) which is added to the DPCM signal d(n), resulting in a sum signal s(n). In an associated receiver, a locally obtained error reduction signal y'(n) is subtracted from this sum signal s'(n) and the difference signal d'(n) thus produced is converted into a local version x'(n) of the information signal. This last-mentioned information signal is quantized in a local error reduction circuit and encoded to produce the local error reduction signal y'(n). In the transmitter, means are also provided for producing a quantization error signal component q(n) which is added to the sum signal s(n) for transmission.

Abstract: In a noise suppression circuit for a video signal the number of elements required can be reduced when a separation circuit (3) for a high-frequency and a low-frequency component is used and the noise suppression is effected in the low-frequency component by means of a comb filter (19) which, in order to realize a still further savings in components, may comprise a delay circuit having a delay (103, 105, 107) which is switchable between a field period plus half a line period and a field period minus half a line period. The noise suppression circuit is therefore particularly suitable for use in television receivers.

Abstract: A television camera comprises a control circuit for controlling the electron beam current intensity in at least one pick-up tube. To prevent oscillations in a positive feedback control loop, a picture signal amplifier in the control loop is provided with a multi-step signal limiter. To this end, for a two-step signal limitation, a diode and a Zener diode have been provided, the junction of which is connected to the base of a biased signal amplifier transistor via a resistor, a second resistor being arranged between the other terminals of the diode and the Zener diode. The junction of the first diode and the second resistor is connected via at least a second diode to the collector of the signal amplifier transistor and the base of an emitter follower transistor connected thereto. The junction of the first Zener diode and the second resistor is connected via a second Zener diode to a voltage terminal.

Abstract: An analog-digital converter supplying a digital output signal in natural or reflected binary code, having an input stage, n consecutive conversion stages comprising two parallel channels of identical structure, in each of which there are two current paths in accordance with the result of a comparison of currents effected in the preceding stage and an output stage to which the switched currents proceed. In the complete converter there are 2.sup.n current paths corresponding to 2.sup.n quantization levels. Conversion is effected by means of a number of stages as small as the number n of bits of the desired digital signal. This converter is simple, fast, asynchronous, has a lower power consumption and its symmetry provides excellent automatic temperature compensation.