Patents by Inventor Marinus Hopstaken

Marinus Hopstaken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11770986
    Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Rozen, Marinus Hopstaken, Yohei Ogawa, Masanobu Hatanaka, Takashi Ando, Kazuhiro Honda
  • Publication number: 20220344586
    Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Inventors: John Rozen, Marinus Hopstaken, Yohei Ogawa, Masanobu Hatanaka, Takashi Ando, Kazuhiro Honda
  • Patent number: 10971626
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10546745
    Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken
  • Publication number: 20190326429
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen w. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10381479
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Publication number: 20190189434
    Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken
  • Patent number: 10304979
    Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin
  • Patent number: 10276384
    Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
  • Publication number: 20190035923
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10134929
    Abstract: Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se absorber layer includes the steps of: providing a reservoir material containing Si or Ge; forming the CZTS/Se absorber layer on the reservoir material; and annealing the reservoir material and the CZTS/Se absorber layer under conditions sufficient to diffuse Si or Ge atoms from the reservoir material into the CZTS/Se absorber layer with a concentration gradient to create band gap grading in the CZTS/Se absorber layer. A photovoltaic device and method of forming the photovoltaic device are also provided.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Richard A. Haight, Marinus Hopstaken, Yun Seog Lee
  • Publication number: 20180218907
    Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 2, 2018
    Applicants: International Business Machines Corporation, Tokyo Electron Limited
    Inventors: Robert L. Bruce, Kevin K Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
  • Publication number: 20180218908
    Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 2, 2018
    Applicants: International Business Machines Corporation, Tokyo Electron Limited
    Inventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
  • Publication number: 20180218909
    Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 2, 2018
    Applicants: International Business Machines Corporation, Tokyo Electron Limited
    Inventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
  • Patent number: 9911879
    Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin
  • Patent number: 9812599
    Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9698339
    Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: July 4, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Anthony J. Annunziata, Marinus Hopstaken, Chandrasekara Kothandaraman, JungHyuk Lee, Deborah A. Neumayer, Jeong-Heon Park
  • Publication number: 20170186943
    Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Anthony J. Annunziata, Marinus Hopstaken, Chandrasekara Kothandaraman, JungHyuk Lee, Deborah A. Neumayer, Jeong-Heon Park
  • Publication number: 20170110606
    Abstract: Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se absorber layer includes the steps of: providing a reservoir material containing Si or Ge; forming the CZTS/Se absorber layer on the reservoir material; and annealing the reservoir material and the CZTS/Se absorber layer under conditions sufficient to diffuse Si or Ge atoms from the reservoir material into the CZTS/Se absorber layer with a concentration gradient to create band gap grading in the CZTS/Se absorber layer. A photovoltaic device and method of forming the photovoltaic device are also provided.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Talia S. Gershon, Richard A. Haight, Marinus Hopstaken, Yun Seog Lee
  • Publication number: 20160225939
    Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.
    Type: Application
    Filed: June 18, 2015
    Publication date: August 4, 2016
    Inventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin