Patents by Inventor Marinus Hopstaken
Marinus Hopstaken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770986Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.Type: GrantFiled: April 22, 2021Date of Patent: September 26, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Rozen, Marinus Hopstaken, Yohei Ogawa, Masanobu Hatanaka, Takashi Ando, Kazuhiro Honda
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Publication number: 20220344586Abstract: A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: John Rozen, Marinus Hopstaken, Yohei Ogawa, Masanobu Hatanaka, Takashi Ando, Kazuhiro Honda
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Patent number: 10971626Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.Type: GrantFiled: July 3, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
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Patent number: 10546745Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.Type: GrantFiled: December 18, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken
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Publication number: 20190326429Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen w. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
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Patent number: 10381479Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.Type: GrantFiled: July 28, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
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Publication number: 20190189434Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken
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Patent number: 10304979Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.Type: GrantFiled: January 30, 2015Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin
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Patent number: 10276384Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.Type: GrantFiled: January 30, 2017Date of Patent: April 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
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Publication number: 20190035923Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
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Patent number: 10134929Abstract: Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se absorber layer includes the steps of: providing a reservoir material containing Si or Ge; forming the CZTS/Se absorber layer on the reservoir material; and annealing the reservoir material and the CZTS/Se absorber layer under conditions sufficient to diffuse Si or Ge atoms from the reservoir material into the CZTS/Se absorber layer with a concentration gradient to create band gap grading in the CZTS/Se absorber layer. A photovoltaic device and method of forming the photovoltaic device are also provided.Type: GrantFiled: October 14, 2015Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Talia S. Gershon, Richard A. Haight, Marinus Hopstaken, Yun Seog Lee
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Publication number: 20180218907Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.Type: ApplicationFiled: January 30, 2017Publication date: August 2, 2018Applicants: International Business Machines Corporation, Tokyo Electron LimitedInventors: Robert L. Bruce, Kevin K Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
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Publication number: 20180218908Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.Type: ApplicationFiled: February 13, 2018Publication date: August 2, 2018Applicants: International Business Machines Corporation, Tokyo Electron LimitedInventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
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Publication number: 20180218909Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.Type: ApplicationFiled: February 13, 2018Publication date: August 2, 2018Applicants: International Business Machines Corporation, Tokyo Electron LimitedInventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Dario L. Goldfarb, Marinus Hopstaken, Mahmoud Khojasteh, George G. Totir, Hongwen Yan, Masahiro Yamazaki
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Patent number: 9911879Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.Type: GrantFiled: June 18, 2015Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin
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Patent number: 9812599Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.Type: GrantFiled: August 3, 2015Date of Patent: November 7, 2017Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoar-Tabari, Marinus Hopstaken, Dae-Gyu Park, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
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Patent number: 9698339Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.Type: GrantFiled: December 29, 2015Date of Patent: July 4, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Anthony J. Annunziata, Marinus Hopstaken, Chandrasekara Kothandaraman, JungHyuk Lee, Deborah A. Neumayer, Jeong-Heon Park
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Publication number: 20170186943Abstract: Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.Type: ApplicationFiled: December 29, 2015Publication date: June 29, 2017Inventors: Anthony J. Annunziata, Marinus Hopstaken, Chandrasekara Kothandaraman, JungHyuk Lee, Deborah A. Neumayer, Jeong-Heon Park
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Publication number: 20170110606Abstract: Techniques for achieving band gap grading in CZTS/Se absorber materials are provided. In one aspect, a method for creating band gap grading in a CZTS/Se absorber layer includes the steps of: providing a reservoir material containing Si or Ge; forming the CZTS/Se absorber layer on the reservoir material; and annealing the reservoir material and the CZTS/Se absorber layer under conditions sufficient to diffuse Si or Ge atoms from the reservoir material into the CZTS/Se absorber layer with a concentration gradient to create band gap grading in the CZTS/Se absorber layer. A photovoltaic device and method of forming the photovoltaic device are also provided.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Inventors: Talia S. Gershon, Richard A. Haight, Marinus Hopstaken, Yun Seog Lee
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Publication number: 20160225939Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.Type: ApplicationFiled: June 18, 2015Publication date: August 4, 2016Inventors: Nestor A. Bojarczuk, Talia S. Gershon, Supratik Guha, Marinus Hopstaken, Byungha Shin