Abstract: A writing-block for writing data to a memory-buffer, wherein the memory-buffer comprises an ordered sequence of elements and the writing-block is configured to: receive an input-data-stream; and write the input-data-stream to the memory-buffer in a successive manner from a first-element of the ordered sequence to a predetermined-element of the ordered sequence. Following writing to the predetermined-element the writing-block is configured to continue to write the input-data-stream to the memory-buffer in a successive manner restarting at the first-element. In response to writing the predetermined-element, the writing-block is configured to also continue to write the input-data-stream to the memory-buffer in a successive manner from an element immediately following the predetermined element until a second predetermined-element of the memory-buffer.

Abstract: A first-transceiver for use in an antenna diversity scheme. The first-transceiver comprises a first-time/clock-generation-unit; a first-receiver; and a first-transmitter. The first-receiver is configured to receive a wireless second-alignment-signal from a second-transceiver with a second-time/clock-generation-unit. The wireless second-alignment-signal is representative of a state of the second-time/clock-generation-unit. The first-transceiver is configured to set the first-time/clock-generation-unit, based on the wireless second-alignment-signal, to reduce an alignment-error between the first-time/clock-generation-unit and the second-time/clock-generation-unit. The first-transmitter is configured to transmit a wireless first-transmission-signal, in accordance with the first-time/clock-generation-unit, as part of the antenna diversity scheme. The first-transmission-signal corresponds to a second-transmission-signal that is transmitted by the second-transceiver.

Abstract: An apparatus is configured to, based on a first signal comprising one or more data transmission frames received from a first radio device by a second radio device. The first signal has a particular carrier frequency of a carrier wave thereof and the one or more data transmission frames comprising a plurality of symbols provided at a particular symbol frequency. The carrier frequency and symbol frequency based on a reference clock frequency of the first radio device. One or more of an estimate of the particular carrier frequency is determined and an estimate of the particular symbol frequency relative to a reference clock frequency of the second radio device and provide for transmission of a response signal from the second radio device to the first radio device.

Abstract: A first-transceiver system for use in an antenna diversity scheme. The first-transceiver system comprising: a first-receiver; a first-time/clock-generation-unit; a first-transmitter; and a timing-controller. The first-receiver is configured to receive a wireless first-common-signal from a third-party-transmitter, wherein the first-common-signal is representative of a common-signal transmitted by the third-party-transmitter. The timing-controller is configured to: receive signaling representative of the first-common-signal; receive signaling representative of a wireless second-common-signal as received at a second-transceiver, the wireless second-common-signal being representative of the common-signal; and generate a timing-signal based on the first-common-signal and the second-common-signal.

Abstract: A first-transceiver system for use in an antenna diversity scheme. The first-transceiver system comprising: a first-receiver; a first-time/clock-generation-unit; a first-transmitter; and a timing-controller. The first-receiver is configured to receive a wireless first-common-signal from a third-party-transmitter, wherein the first-common-signal is representative of a common-signal transmitted by the third-party-transmitter. The timing-controller is configured to: receive signaling representative of the first-common-signal; receive signaling representative of a wireless second-common-signal as received at a second-transceiver, the wireless second-common-signal being representative of the common-signal; and generate a timing-signal based on the first-common-signal and the second-common-signal.

Abstract: A first-transceiver for use in an antenna diversity scheme. The first-transceiver comprises a first-time/clock-generation-unit; a first-receiver; and a first-transmitter. The first-receiver is configured to receive a wireless second-alignment-signal from a second-transceiver with a second-time/clock-generation-unit. The wireless second-alignment-signal is representative of a state of the second-time/clock-generation-unit. The first-transceiver is configured to set the first-time/clock-generation-unit, based on the wireless second-alignment-signal, to reduce an alignment-error between the first-time/clock-generation-unit and the second-time/clock-generation-unit. The first-transmitter is configured to transmit a wireless first-transmission-signal, in accordance with the first-time/clock-generation-unit, as part of the antenna diversity scheme. The first-transmission-signal corresponds to a second-transmission-signal that is transmitted by the second-transceiver.

Abstract: A first-transceiver system for use in an antenna diversity scheme. The first-transceiver system comprising: a first-receiver; a first-time/clock-generation-unit; a first-transmitter; and a timing-controller. The first-receiver is configured to receive a wireless first-common-signal from a third-party-transmitter, wherein the first-common-signal is representative of a common-signal transmitted by the third-party-transmitter. The timing-controller is configured to: receive signaling representative of the first-common-signal; receive signaling representative of a wireless second-common-signal as received at a second-transceiver, the wireless second-common-signal being representative of the common-signal; and generate a timing-signal based on the first-common-signal and the second-common-signal.

Abstract: A writing-block for writing data to a memory-buffer, wherein the memory-buffer comprises an ordered sequence of elements and the writing-block is configured to: receive an input-data-stream; and write the input-data-stream to the memory-buffer in a successive manner from a first-element of the ordered sequence to a predetermined-element of the ordered sequence. Following writing to the predetermined-element the writing-block is configured to continue to write the input-data-stream to the memory-buffer in a successive manner restarting at the first-element. In response to writing the predetermined-element, the writing-block is configured to also continue to write the input-data-stream to the memory-buffer in a successive manner from an element immediately following the predetermined element until a second predetermined-element of the memory-buffer.

Abstract: Embodiments include a method of adding first and second binary numbers having C bits and divided into D words to provide a third binary number in E successive adding operations, C, D and E being plural positive integers, the method comprising: a first group of D adding operations adding together respective words of the first and second binary numbers to provide D sum and carry outputs ranging from a least significant to a most significant sum and carry output; one or more subsequent groups of adding operations adding together sum and carry outputs from an immediately preceding group of adding operations, a final group of the one or more subsequent groups resulting in the third binary number consisting of the sum outputs from the final group and a carry from the most significant carry output of the final group, wherein E is less than D.

Abstract: A method of processing a signal by non-uniform quantization of log likelihood ratios is disclosed. A method comprising the steps of: receiving a plurality of bits; calculating a log likelihood ratio, known as a LLR, for each bit; providing a LLR value for each bit based on the calculated LLR; quantizing the LLR values into a plurality of quantization bins, each quantization bin having: a width representative of one or more LLR values; and an index value having a bit length; and associating each bit with the index value that corresponds to its LLR value, wherein the width of each quantization bin is non-uniform. This compresses the LLR values in a more efficient manner, requiring lower memory usage and/or lower bandwidth. A chip for a receiver and a communication system comprising one or more receivers are also disclosed.

Abstract: An apparatus is configured to, based on a first signal comprising one or more data transmission frames received from a first radio device by a second radio device. The first signal has a particular carrier frequency of a carrier wave thereof and the one or more data transmission frames comprising a plurality of symbols provided at a particular symbol frequency. The carrier frequency and symbol frequency based on a reference clock frequency of the first radio device. One or more of an estimate of the particular carrier frequency is determined and an estimate of the particular symbol frequency relative to a reference clock frequency of the second radio device and provide for transmission of a response signal from the second radio device to the first radio device.

Abstract: Embodiments include a method of adding first and second binary numbers having C bits and divided into D words to provide a third binary number in E successive adding operations, C, D and E being plural positive integers, the method comprising: a first group of D adding operations adding together respective words of the first and second binary numbers to provide D sum and carry outputs ranging from a least significant to a most significant sum and carry output; one or more subsequent groups of adding operations adding together sum and carry outputs from an immediately preceding group of adding operations, a final group of the one or more subsequent groups resulting in the third binary number consisting of the sum outputs from the final group and a carry from the most significant carry output of the final group, wherein E is less than D.

Abstract: A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.

Abstract: A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.

Abstract: A method of processing a signal by non-uniform quantization of log likelihood ratios is disclosed. In particular a disclosed method comprising the steps of: receiving (110) a plurality of bits (12); calculating (120) a log likelihood ratio (22), known as a LLR, for each bit; providing (130) a LLR value (22) for each bit based on the calculated LLR; quantizing (140) the LLR values into a plurality of quantization bins, each quantization bin having: a width representative of one or more LLR values; and an index value (32) having a bit length; and associating (150) each bit with the index value (32) that corresponds to its LLR value (22), wherein the width of each quantization bin is non-uniform. This compresses the LLR values (22) in a more efficient manner, requiring lower memory usage and/or lower bandwidth. A chip for a receiver and a communication system comprising one or more receivers are also disclosed.

Abstract: A line-based one-dimensional system and method for video and graphic compression compresses an image data block that contains image data values from one or more neighboring pixels. The system and method involves compressing an image data sample of the image data block using multiple different compression techniques to generate multiple compression results, selecting one of the compression results, and compressing a next image data sample using the multiple different compression techniques and a compression error from the selected one of the compression results.

Abstract: A line-based one-dimensional system and method for video and graphic compression compresses an image data block that contains image data values from one or more neighboring pixels. The system and method involves compressing an image data sample of the image data block using multiple different compression techniques to generate multiple compression results, selecting one of the compression results, and compressing a next image data sample using the multiple different compression techniques and a compression error from the selected one of the compression results.

Abstract: A line-based one-dimensional system and method for video and graphic compression compresses an image data block that contains image data values from one or more neighboring pixels. The system and method involves compressing an image data sample of the image data block using multiple different compression techniques to generate multiple compression results, selecting one of the compression results, and compressing a next image data sample using the multiple different compression techniques and a compression error from the selected one of the compression results.

Abstract: A testable processor system (10,20) comprises a plurality of modules (11, 12, . . . In). Each module (11) comprises a processor unit (110) and a debug controller (111). The debug controllers are coupled to a common test access point controller (TAP-controller 20), and have a test data input (Tin), a test data output (Tout) and at least one test register (112, 113). The test data inputs and outputs of the debug controllers (111, 121, 131, . . . , InI) are arranged in a scan chain having an input for receiving test input data (TDI) from the TAP-controller and an output for providing test output data (TDO) to the TAP-controller. At least one debug controller (111) has a selection facility (115) to select whether data in the scanchain is either shifted through the at least one test register (112) of that debug controller (111) or is immediately forwarded from the test data input (Tin) to the test data output (Tout) of that debug controller.

Abstract: A display device (506) is driven in a number of sub-fields. Each of the sub-fields is for outputting a respective illumination level by the display device. In each sub-field, a pixel of the displayed image may emit an amount of light corresponding to the particular sub-field, depending on whether it is switched on or not. A required intensity level of the pixel is realized by selecting an appropriate combination of sub-fields in which the pixel is switched on. A selection is made from the possible intensity levels that can be generated by all possible combinations of sub-fields. This selection contains those intensity levels that can be generated by sub-fields that are temporally close together, thus causing that the light of a pixel is emitted during a relatively short period. The image display unit (300) has a look-up table (306) for storing the combinations of sub-fields for the respective selected intensity levels.